MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 163

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Modes of Operation
6.8.3
Stop4: Low Voltage Detect or BDM Enabled in Stop Mode
Stop4 is differentiated from stop2 and stop3 in that the on-chip regulator is fully engaged.
Entry into halt mode from run mode is enabled if the XCSR[ENBDM] bit is set. This register is described
in
Chapter 26, “Version 1 ColdFire Debug (CF1_DEBUG)”.
If XCSR[ENBDM] is set when the CPU
executes a STOP instruction, the system clocks to the background debug logic remain active when the
MCU enters stop mode. Because of this, background debug communication remains possible. If you
attempt to enter stop2 or stop3 with XCSR[ENBDM] set, the MCU enters stop4 instead (see
Table 6-1
for
details).
Stop4 is also entered if SPMSC1[LVDE, LVDSE] are set, enabling low voltage detect when the STOP
instruction is executed. The LVD may only be used when the on-chip regulator is in full regulation mode.
Thus, stop3 and stop2 modes are not compatible with use of the LVD.
The LVD system is capable of generating an interrupt or a reset when the supply voltage drops below the
LVD voltage.
Stop4 can be exited by asserting RESET or by an interrupt from one of the following sources: the
PRACMP, IRTC, LVD, LVW, ADC, IRQ, SCI, LCD or the KBI. The following modules are inactive in
stop4: SPI, IIC, MTIM, MTIM16, PDB, and TPM.
6.9
On-Chip Peripheral Modules in Stop and Low-Power Modes
When the MCU enters any stop mode (wait not included), peripheral clocks to the internal peripheral
modules are stopped. Even in the exception case (XCSR[ENBDM] = 1), where clocks to the background
debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption.
One exception to the above is that the crystal oscillator can continue to run, and can be used by the LCD
module to maintain an LCD display, even during STOP2.
Refer to
Section 6.8.1, “Stop2 Mode,”
for specific information on system behavior in stop modes.
When the MCU enters LPwait or LPrun modes, system clocks to the internal peripheral modules continue
based on the settings of the clock gating control registers (SCGC1-5).
Table 6-3
defines terms used in
Table 6-4
to describe operation of components on the chip in the various
low-power modes.
Table 6-3. Term Definition for
Table 6-4
1
Voltage Regulator
Clocked
Not Clocked
Full Regulation
FullOn
FullNoClk
2
FullADACK
3
Loose Regulation
SoftOn
SoftNoClk
Disabled
4
SoftADACK
Off
N/A
Off
1
Subject to module enables and settings of System Clock Gating Control Registers (SCGC1– SCGC5).
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor
6-11