MC9S12C96MFAE Freescale Semiconductor, MC9S12C96MFAE Datasheet - Page 181
![IC MCU 96K FLASH 4K RAM 48-LQFP](/photos/12/38/123817/mc9s12c96mfae_sml.jpg)
MC9S12C96MFAE
Manufacturer Part Number
MC9S12C96MFAE
Description
IC MCU 96K FLASH 4K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C96MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C96MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Figure 6-9
target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of
the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Because the
target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly
drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after
starting the bit time.
Freescale Semiconductor
TARGET SYSTEM
TARGET SYSTEM
SPEEDUP PULSE
TARGET SYS.
START OF BIT TIME
TARGET SYS.
START OF BIT TIME
BKGD PIN
DRIVE AND
BKGD PIN
SPEEDUP
DRIVE TO
BKGD PIN
DRIVE TO
BKGD PIN
CLOCK
CLOCK
PULSE
HOST
PERCEIVED
HOST
shows the host receiving a logic 0 from the target. Because the host is asynchronous to the
PERCEIVED
Figure 6-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 6-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
HIGH-IMPEDANCE
10 CYCLES
MC9S12C-Family / MC9S12GC-Family
10 CYCLES
R-C RISE
10 CYCLES
10 CYCLES
Rev 01.24
Chapter 6 Background Debug Module (BDMV4) Block Description
HIGH-IMPEDANCE
HOST SAMPLES
HIGH-IMPEDANCE
HOST SAMPLES
BKGD PIN
BKGD PIN
SPEEDUP PULSE
HIGH-IMPEDANCE
EARLIEST
START OF
NEXT BIT
EARLIEST
START OF
NEXT BIT
181
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