MC9S12C96MFAE Freescale Semiconductor, MC9S12C96MFAE Datasheet - Page 422
![IC MCU 96K FLASH 4K RAM 48-LQFP](/photos/12/38/123817/mc9s12c96mfae_sml.jpg)
MC9S12C96MFAE
Manufacturer Part Number
MC9S12C96MFAE
Description
IC MCU 96K FLASH 4K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C96MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C96MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description
14.3.2.4
Read: anytime
Write: has no effect
14.3.2.5
Read: anytime; normally read only after SPIF is set
422
Module Base 0x0003
Module Base 0x0005
SPTEF
Reset
Reset
MODF
Field
SPIF
7
5
4
W
W
R
R
SPIF
SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI Data Register.
This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI Data
Register.
0 Transfer not yet complete
1 New data copied to SPIDR
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear
this bit and place data into the transmit data register, SPISR has to be read with SPTEF = 1, followed by a write
to SPIDR. Any write to the SPI Data Register without reading SPTEF = 1, is effectively ignored.
0 SPI Data register not empty
1 SPI Data register empty
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 14.3.2.2, “SPI Control Register 2 (SPICR2).”
Register (with MODF set) followed by a write to the SPI Control Register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
Bit 7
SPI Status Register (SPISR)
SPI Data Register (SPIDR)
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
6
0
6
6
Figure 14-6. SPI Status Register (SPISR)
Figure 14-7. SPI Data Register (SPIDR)
Table 14-8. SPISR Field Descriptions
SPTEF
MC9S12C-Family / MC9S12GC-Family
1
5
0
5
5
MODF
Rev 01.24
0
4
0
4
4
Description
The flag is cleared automatically by a read of the SPI Status
0
0
3
0
3
3
0
0
2
0
2
2
Freescale Semiconductor
0
0
2
0
1
1
Bit 0
0
0
0
0
0
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