MC9S12C96MFAE Freescale Semiconductor, MC9S12C96MFAE Datasheet - Page 86
![IC MCU 96K FLASH 4K RAM 48-LQFP](/photos/12/38/123817/mc9s12c96mfae_sml.jpg)
MC9S12C96MFAE
Manufacturer Part Number
MC9S12C96MFAE
Description
IC MCU 96K FLASH 4K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C96MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C96MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.2.3
Read: Anytime.
Write: Anytime.
86
Module Base + 0x000A
DDRS[3:0]
Reset
Field
3–0
W
R
Direction Register Port S — This register configures each port S pin as either input or output.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is
forced to be an output if the SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel
is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTS
0
0
7
Port S Data Direction Register (DDRS)
or PTIS registers, when changing the DDRS register.
= Unimplemented or Reserved
0
0
6
Figure 2-12. Port S Data Direction Register (DDRS)
Table 2-11. DDRS Field Descriptions
MC9S12C-Family / MC9S12GC-Family
0
0
5
Rev 01.24
0
0
4
Description
DDRS3
0
3
DDRS2
0
2
DDRS1
Freescale Semiconductor
0
1
DDRS0
0
0
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