DF2211CUNP24V Renesas Electronics America, DF2211CUNP24V Datasheet - Page 168

MCU 16BIT FLASH 3V 64K 64-QFN

DF2211CUNP24V

Manufacturer Part Number
DF2211CUNP24V
Description
MCU 16BIT FLASH 3V 64K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of DF2211CUNP24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2211CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
135
5.7
5.7.1
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.8 shows an example in which the TGIEA bit in the TPU's TIER_0 is cleared to 0.
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Rev.7.00 Dec. 24, 2008 Page 112 of 698
REJ09B0074-0700
Internal
address bus
Internal
write signal
TGIEA
TGFA
TGI0A
Interrupt signal
Usage Notes
Contention between Interrupt Generation and Disabling
φ
Figure 5.8 Contention between Interrupt Generation and Disabling
TIER0 write cycle by CPU
TIER_0 address
TGI0A exception handling

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