M30280F6HP#D5 Renesas Electronics America, M30280F6HP#D5 Datasheet - Page 135

• Manufacturer Part Number: M30280F6HP#D5
• Description: IC M16C MCU FLASH 48K 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
Figure 12.13 Example of 16-bit Pulse Width Modulator Operation
Figure 12.14 Example of 8-bit Pulse Width Modulator Operation
. v
J
6
0
C
2
9
2 /
0 .
B
0
8
0
0
NOTES:
Underflow signal of
8-bit prescaler
IR bit of TAiIC
register
f
i = 0 to 4
Count source
Input signal to
TA
PWM pulse output
from TA
G
j
4
J
: Frequency of count source
7
a
o r
NOTES:
iIN
1. The 8-bit prescaler counts the count source.
2. The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
3. m = 00
4. This timing diagram is for the case where the TAi register is "0202
f
i = 0 to 4
j
(f
0 -
. n
PWM pulse output
from TA
IR bit of TAiIC
register
Count source
Input signal to
TA
: Frequency of count source
1
or TRGSR register is set to "00
the MR2 bit in the TAiMR register is set to "1" (trigger selected by TAiTGH and TAiTGL bits).
u
1. n = 0000
2. This timing diagram is for the case where the TAi register is "0003
pin
, f
2
(f
3
iIN
p
0
ONSF or TRGSR register is set to "00
edge), and the MR2 bit in the TAiMR register is set to "1" (trigger selected by TAiTGH and TAiTGL bits).
2
1
iOUT
, 1
, f
0
, f
(
pin
M
8
2
2
, f
, f
iOUT
16
0
pin
1
32
8
(1)
0
6
, f
(2)
to FF
, f
7
C
pin
32
16
C32
2 /
, f
to FFFE
16
C32
)
page 113
, 8
; n = 00
)
“H”
“H”
“H”
“1”
“0”
“L”
“L”
“L”
M
“H”
“H”
“L”
“L”
“1”
“0”
1
16
6
.
16
C
2 /
to FE
f o
8
3
) B
2
8
"(TAi
16
5
.
IN
pin input), the MR1 bit in the TAiMR register is set to "0" (falling edge), and
Set to “0” upon accepting an interrupt request or by program
2
" (TAi
Set to “0” upon accepting an interrupt request or by program
IN
Trigger is not generated by this signal
pin input), the MR1 bit in the TAiMR register is set to "1" (rising
1 / f
1 / f
1 / f
j
i
X (m + 1)
1 / f
j
X
1 / f
X
(2
n
j
j
16
X (m + 1) X (2 – 1)
X (m + 1) X n
– 1)
16
", the TAiTGH and TAiTGL bits in the ONSF
16
", the TAiTGH and TAiTGL bits in the
8
12. Timer