M30280F6HP#D5 Renesas Electronics America, M30280F6HP#D5 Datasheet - Page 208

• Manufacturer Part Number: M30280F6HP#D5
• Description: IC M16C MCU FLASH 48K 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
Figure 14.16 Typical transmit timing in UART mode (UART0, UART1)
. v
J
6
0
C
2
9
2 /
0 .
The above timing diagram applies to the case where the register bits are set
as follows:
B
• Example of transmit timing when transfer data is 8-bit long (parity enabled, one stop bit)
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
CTSi
TxDi
UiC0 register
TXEPT bit
SiTIC register
IR bit
The above timing diagram applies to the case where the register bits are set
as follows:
• Example of transmit timing when transfer data is 9-bit long (parity disabled, two stop bits)
Transfer clock
TxDi
UiC1 register
TE bit
UiC1 register
TI bit
UiC0 register
TXEPT bit
SiTIC register
IR bit
• Set the PRYE bit in the UiMR register to "1" (parity enabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTS/RTS enabled),
• Set the UiIRS bit to "1" (an interrupt request occurs when transmit completed):
0
8
• Set the PRYE bit in the UiMR register to "0" (parity disabled)
• Set the STPS bit in the UiMR register to "1" (2 stop bits)
• Set the CRD bit in the UiC0 register to "1"(CTS/RTS disabled)
• Set the UiIRS bit to "0" (an interrupt request occurs when transmit buffer
0
the CRS bit to "0" (CTS selected)
0
becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
G
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
4
J
7
a
o r
0 -
. n
u
2
3
p
0
, 1
0
(
M
2
0
1
“H”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
0
“1”
“0”
“1”
“0”
“L”
“1”
“0”
“1”
“0”
6
7
C
2 /
page 186
, 8
M
Start
ST
bit
Start
ST
1
bit
6
D
Write data to the UiTB register
0
C
D
Write data to the UiTB register
Cleared to “0” when interrupt request is accepted, or cleared to “0” by program
0
D
2 /
f o
1
D
8
1
D
Tc
3
) B
2
8
D
2
5
D
3
D
3
Tc
D
4
D
4
D
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
5
D
5
D
6
D
6
D
7
Transferred from UiTB register to UARTi transmit register
D
7
Parity
D
bit
8
Stop
P
bit
SP
Cleared to “0” when interrupt request is accepted, or cleared to “0” by program
SP
Stop
bit
SP
Stop
bit
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
ST
ST
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
D
Transferred from UiTB register to UARTi
transmit register
i: 0 to 2
fj : frequency of UiBRG count source (f
f
n : value set to UiBRG
D
EXT
0
0
fj : frequency of UiBRG count source (f
f
n : value set to UiBRG
i: 0 to 2
EXT
D
D
1
: frequency of UiBRG count source (external clock)
1
: frequency of UiBRG count source (external clock)
D
D
2
2
D
D
3
3
D
D
4
4
D
D
5
5
D
D
6
6
D
D
EXT
7
7
EXT
D
P SP
8
SPSP
1SIO
1SIO
Stopped pulsing
because the TE bit
= “0”
ST
, f
2SIO
, f
2SIO
D
ST
0
, f
D
8SIO
, f
D
1
8SIO
0
, f
D
1
32SIO
, f
14.Serial I/O
32SIO
)
)