MCF5208CAB166 Freescale Semiconductor, MCF5208CAB166 Datasheet - Page 32
![MCU 32BIT 166.67MHZ 160-QFP](/photos/31/38/313814/160pin_pqfp_sml.jpg)
MCF5208CAB166
Manufacturer Part Number
MCF5208CAB166
Description
MCU 32BIT 166.67MHZ 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF520xr
Datasheet
1.MCF5207CVM166J.pdf
(46 pages)
Specifications of MCF5208CAB166
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
166.67MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
166.67MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.6/1.95/2.75/3.6V
Operating Supply Voltage (min)
1.4/1.7/2.25/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
160
Package Type
PQFP
Processor Series
MCF520x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5208CAB166
Manufacturer:
SANREX
Quantity:
210
Company:
Part Number:
MCF5208CAB166
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
7
8
9
Electrical Characteristics
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes
valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
32
SD_DQS3/SD_DQS2
SD_RAS, SD_CAS
SD_CSn, SD_WE,
D[31:24]/D[23:16]
DM3/DM2
SD_CLK
SD_CLK
A[13:0]
DD4
MCF5208 ColdFire
CMD
ROW
DD1
Figure 18. DDR Write Timing
DD5
®
Microprocessor Data Sheet, Rev. 3
COL
DD6
WD1 WD2 WD3 WD4
DD2
DD3
DD7
DD7
DD8
DD8
Freescale Semiconductor