MCF5208CAB166 Freescale Semiconductor, MCF5208CAB166 Datasheet - Page 44

• Manufacturer Part Number: MCF5208CAB166
• Description: MCU 32BIT 166.67MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF520xr

Specifications of MCF5208CAB166

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 166.67MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 166.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Processor Series: MCF520x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Revision History
44
Revision
Number
0.4
0.5
0.6
1
2
3
10/10/2005
3/29/2006
7/21/2006
3/28/2007
12/4/2008
9/1/2009
Date
MCF5208 ColdFire
Table 26. Revision History (continued)
Changed the following specs in
•
•
•
• Added “top view” and “bottom view” labels where appropriate to
• Updated mechanical drawings to latest available, and added note to
• Corrected cross-reference to
• Corrected L3 label in
• Corrected L6 label in
• Removed second sentence from
• Removed third and fourth paragraphs from
• Removed preliminary designation from
• Updated
• Updated
• Added
• Updated
• Made some corrections to the drawings in
• Edited for grammar, punctuation, spelling, style, and format. - JD
• Updated FlexBus read and write timing diagrams in
• Minimum frequency of operation from TBD to 60MHz
• Maximum clock period from TBD to 16.67 ns
• Changed doc type from Advance Information to Technical Data
Figure 1
Figure 4
Figure 6
from TEST to VSS
mechanical drawings and pinouts.
Section 4, “Mechanicals and Pinouts.”
MAPBGA.”
SD_DQS1 to SD_DQS3.
Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK),”
regarding no minimum frequency requirement for TXCLK.
Signal Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK),”
as this feature is not supported on this device.
Characteristics.”
Figure
®
Microprocessor Data Sheet, Rev. 3
15.
Section 5.5, “Current Consumption.”
and
and
and
Section 5.2, “Thermal Characteristics.”
Section 5.4, “DC Electrical Specifications.”
Section 5.6, “Oscillator and PLL Electrical Characteristics.”
Table
Table
Table
3: Changed pin 39 from EVDD to SD_VDD and pin 117
3: Changed pin 33 from EVDD to SD_VDD
3: Changed ball D10 from TEST to VSS
Figure 9
Figure 9
Substantive Changes
Table 12
Figure 9
from SD_DQS0 to SD_DQS2 and H3 from
from SD_DR_DQS to SD_SDR_DQS.
Section 5.12.2, “MII Transmit Signal
and
in
Section 5, “Electrical
Section 4.7, “Pinout—196
Section 5.8, “SDRAM Bus.”
Table
Section 5.12.2, “MII Transmit
13:
Freescale Semiconductor
Figure 14
and