HD64F3687GH Renesas Electronics America, HD64F3687GH Datasheet - Page 87

• Manufacturer Part Number: HD64F3687GH
• Description: IC H8 MCU FLASH 56K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GH

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.2.4
IENR2 enables, timer B1 overflow interrupts.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
3.2.5
IRR1 is a status flag register for direct transition interrupts, RTC interrupts, and IRQ3 to IRQ0
interrupt requests.
Bit
7, 6
5
4 to 0
Bit
7
6
Bit Name
IENTB1
Bit Name
IRRDT
IRRTA
Interrupt Enable Register 2 (IENR2)
Interrupt Flag Register 1 (IRR1)
Initial
Value
All 0
0
All 1
Initial
Value
0
0
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0.
Timer B1 Interrupt Enable
When this bit is set to 1, timer B1 overflow interrupt
requests are enabled.
Reserved
These bits are always read as 1.
Description
Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
RTC Interrupt Request Flag
[Setting condition]
When the RTC counter value overflows
[Clearing condition]
When IRRTA is cleared by writing 0
Rev.5.00 Nov. 02, 2005 Page 53 of 500
Section 3 Exception Handling
REJ09B0027-0500