MCF5270CVM150J Freescale Semiconductor, MCF5270CVM150J Datasheet - Page 13
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MCF5270CVM150J
Manufacturer Part Number
MCF5270CVM150J
Description
IC MCU 166MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CVM150J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
97
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CVM150J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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12.2
12.3
12.3.1
12.3.1.1
12.3.1.2
12.3.1.3
12.3.1.4
12.3.1.5
12.3.1.6
12.3.1.7
12.4
12.4.1
12.4.2
12.5
13.1
13.1.1
13.1.2
13.1.2.1
13.1.2.2
13.1.2.3
13.2
13.2.1
13.2.1.1
13.2.1.2
13.2.1.3
13.2.1.4
13.2.1.5
13.2.1.6
13.2.1.7
13.3
14.1
14.1.1
Freescale Semiconductor
Paragraph
Number
External Signal Description .......................................................................................... 12-3
Memory Map/Register Definition ................................................................................ 12-9
Functional Description................................................................................................ 12-31
Initialization/Application Information ........................................................................ 12-32
Introduction................................................................................................................... 13-1
Memory Map/Register Definition ................................................................................ 13-4
Low-Power Wakeup Operation .................................................................................. 13-15
Introduction................................................................................................................... 14-1
Register Descriptions.............................................................................................. 12-10
Overview................................................................................................................. 12-31
Port Digital I/O Timing........................................................................................... 12-32
68K/ColdFire Interrupt Architecture Overview ....................................................... 13-1
Interrupt Controller Theory of Operation ................................................................. 13-2
Register Descriptions................................................................................................ 13-6
Overview................................................................................................................... 14-1
Port Output Data Registers (PODR_x) ............................................................... 12-10
Port Data Direction Registers (PDDR_x) ........................................................... 12-12
Port Pin Data/Set Data Registers (PPDSDR_x).................................................. 12-14
Port Clear Output Data Registers (PCLRR_x) ................................................... 12-16
Pin Assignment Registers (PAR_x).................................................................... 12-18
Timer Pin Assignment Registers (PAR_TIMERH & PAR_TIMERL).............. 12-26
Drive Strength Control Registers (DSCR_x)...................................................... 12-27
Interrupt Recognition............................................................................................ 13-3
Interrupt Prioritization .......................................................................................... 13-3
Interrupt Vector Determination ............................................................................ 13-4
Interrupt Pending Registers (IPRH, IPRL)........................................................... 13-6
Interrupt Mask Register (IMRH, IMRL) .............................................................. 13-7
Interrupt Force Registers (INTFRCH, INTFRCL)............................................... 13-9
Interrupt Request Level Register (IRLR) ........................................................... 13-11
Interrupt Acknowledge Level and Priority Register (IACKLPR)...................... 13-11
Interrupt Control Register (ICRx, (x = 1, 2,..., 63)) ............................................ 13-12
Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)......... 13-14
Interrupt Controller Modules
MCF5271 Reference Manual, Rev. 2
DMA Controller Module
Contents
Chapter 13
Chapter 14
Title
Number
Page
xiii
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