MCF5270CVM150J Freescale Semiconductor, MCF5270CVM150J Datasheet - Page 16
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MCF5270CVM150J
Manufacturer Part Number
MCF5270CVM150J
Description
IC MCU 166MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CVM150J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
97
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CVM150J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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18.1
18.1.1
18.1.2
18.1.2.1
18.1.3
18.2
18.3
18.3.1
18.3.2
18.3.3
18.3.4
18.3.4.1
18.3.4.2
18.3.4.3
18.3.4.4
18.3.4.5
18.3.5
18.3.5.1
18.4
18.4.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.6
19.1
19.1.1
19.1.2
19.1.3
19.1.4
19.1.4.1
19.1.5
19.1.5.1
19.1.5.2
xvi
Paragraph
Number
Introduction................................................................................................................... 18-1
External Signal Description .......................................................................................... 18-4
Memory Map/Register Definition ................................................................................ 18-5
SDRAM Example ....................................................................................................... 18-20
Introduction................................................................................................................... 19-1
Block Diagram.......................................................................................................... 18-1
Overview................................................................................................................... 18-3
Operation .................................................................................................................. 18-3
DRAM Control Register (DCR) ............................................................................... 18-5
DRAM Address and Control Registers (DACR0/DACR1) ..................................... 18-6
DRAM Controller Mask Registers (DMR0/DMR1) ................................................ 18-9
General Synchronous Operation Guidelines............................................................. 18-9
Initialization Sequence............................................................................................ 18-18
SDRAM Interface Configuration............................................................................ 18-20
DCR Initialization................................................................................................... 18-21
DACR Initialization................................................................................................ 18-21
DMR Initialization.................................................................................................. 18-23
Mode Register Initialization ................................................................................... 18-24
Initialization Code................................................................................................... 18-25
Overview................................................................................................................... 19-1
Block Diagram.......................................................................................................... 19-1
Features..................................................................................................................... 19-3
Modes of Operation .................................................................................................. 19-4
Interface Options....................................................................................................... 19-4
Definitions ............................................................................................................ 18-3
Address Multiplexing ........................................................................................... 18-9
Interfacing Example............................................................................................ 18-14
Burst Page Mode................................................................................................. 18-14
Auto-Refresh Operation...................................................................................... 18-16
Self-Refresh Operation ....................................................................................... 18-17
Mode Register Settings....................................................................................... 18-19
Full and Half Duplex Operation ........................................................................... 19-4
10 Mbps and 100 Mbps MII Interface.................................................................. 19-4
10 Mpbs 7-Wire Interface Operation.................................................................... 19-5
Synchronous DRAM Controller Module
Fast Ethernet Controller (FEC)
MCF5271 Reference Manual, Rev. 2
Contents
Chapter 18
Chapter 19
Title
Freescale Semiconductor
Number
Page
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