MCF5270CVM150J Freescale Semiconductor, MCF5270CVM150J Datasheet - Page 382
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MCF5270CVM150J
Manufacturer Part Number
MCF5270CVM150J
Description
IC MCU 166MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CVM150J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
97
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CVM150J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Fast Ethernet Controller (FEC)
If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller
follows the specified backoff procedures and attempts to retransmit the frame until the retry limit
is reached. The transmit FIFO stores at least the first 64 bytes of the transmit frame, so that they
do not have to be retrieved from system memory in case of a collision. This improves bus
utilization and latency in case immediate retransmission is necessary.
When all the frame data has been transmitted, the FCS (Frame Check Sequence or 32-bit Cyclic
Redundancy Check, CRC) bytes are appended if the TC bit is set in the transmit frame control
word. If the ABC bit is set in the transmit frame control word, a bad CRC will be appended to the
frame data regardless of the TC bit value. Following the transmission of the CRC, the Ethernet
controller writes the frame status information to the MIB block. Short frames are automatically
padded by the transmit logic (if the TC bit in the transmit buffer descriptor for the end of frame
buffer = 1).
Both buffer (TXB) and frame (TFINT) interrupts may be generated as determined by the settings
in the EIMR.
The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and
XFIFO_UN. If the transmit frame length exceeds MAX_FL bytes the BABT interrupt will be
asserted, however the entire frame will be transmitted (no truncation).
To pause transmission, set the GTS (graceful transmit stop) bit in the TCR register. When the
TCR[GTS] is set, the FEC transmitter stops immediately if transmission is not in progress;
otherwise, it continues transmission until the current frame either finishes or terminates with a
collision. After the transmitter has stopped the GRA (graceful stop complete) interrupt is asserted.
If TCR[GTS] is cleared, the FEC resumes transmission with the next frame.
The Ethernet controller transmits bytes least significant bit first.
19.3.7 FEC Frame Reception
The FEC receiver is designed to work with almost no intervention from the host and can perform
address recognition, CRC checking, short frame checking, and maximum frame length checking.
When the driver enables the FEC receiver by setting ECR[ETHER_EN], it will immediately start
processing receive frames. When ERXDV is asserted, the receiver will first check for a valid
PA/SFD header. If the PA/SFD is valid, it will be stripped and the frame will be processed by the
receiver. If a valid PA/SFD is not found, the frame will be ignored.
In serial mode, the first 16 bit times of RX_D0 following assertion of ERXDV are ignored.
Following the first 16 bit times the data sequence is checked for alternating 1/0s. If a 11 or 00 data
sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time
21, the data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected.
When a 11 is detected, the PA/SFD sequence is complete.
MCF5271 Reference Manual, Rev. 2
19-38
Freescale Semiconductor
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