C8051F067-GQ Silicon Laboratories Inc, C8051F067-GQ Datasheet - Page 179

• Manufacturer Part Number: C8051F067-GQ
• Description: IC 8051 MCU 32K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F067-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 1 Channel
• On-chip Dac: 12 bit, 2 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1222

C8051F060/1/2/3/4/5/6/7
16.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as prevent the viewing of proprietary program code and constants. The Program Store Write
Enable (PSCTL.0) and the Program Store Erase Enable (PSCTL.1) bits protect the Flash memory from
accidental modification by software. These bits must be explicitly set to logic 1 before software can write or
erase the Flash memory. Additional security features prevent proprietary program code and data constants
from being read or altered across the JTAG interface or by software running on the system controller.
A set of security lock bytes protect the Flash program memory from being read or altered across the JTAG
interface. Each bit in a security lock-byte protects one 8k-byte block of memory. Clearing a bit to logic 0 in
a Read Lock Byte prevents the corresponding block of Flash memory from being read across the JTAG
interface. Clearing a bit in the Write/Erase Lock Byte protects the block from JTAG erasures and/or writes.
The Scratchpad area is read or write/erase locked when all bits in the corresponding security byte are
cleared to logic 0.
On the C8051F060/1/2/3/4/5, the security lock bytes are located at 0xFBFE (Write/Erase Lock) and
0xFBFF (Read Lock), as shown in Figure 16.1. On the C8051F066/7, the security lock bytes are located at
0x7FFE (Write/Erase Lock) and 0x7FFF (Read Lock), as shown in Figure 16.2. The 512-byte sector con-
taining the lock bytes can be written to, but not erased, by software. An attempted read of a read-locked
byte returns undefined data. Debugging code in a read-locked sector is not possible through the JTAG
interface. The lock bits can always be read from and written to logic 0 regardless of the security setting
applied to the block containing the security bytes. This allows additional blocks to be protected after the
block containing the security bytes has been locked.
Important Note: To ensure protection from external access, the block containing the lock bytes
must be Write/Erase locked. On the 64 k byte devices (C8051F060/1/2/3/4/5), the page containing
the security bytes is 0xFA00-0xFBFF, and is locked by clearing bit 7 of the Write/Erase Lock Byte.
On the 32 k byte devices (C8051F066/7), the page containing the security bytes is 0x7E00-0x7FFF,
and is locked by clearing bit 3 of the Write/Erase Lock Byte. If the page containing the security
bytes is not Write/Erase locked, it is still possible to erase this page of Flash memory through the
JTAG port and reset the security bytes.
When the page containing the security bytes has been Write/Erase locked, a JTAG full device erase
must be performed to unlock any areas of Flash protected by the security bytes. A JTAG full
device erase is initiated by performing a normal JTAG erase operation on either of the security byte
locations. This operation must be initiated through the JTAG port, and cannot be performed from
firmware running on the device.
Rev. 1.2
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