C8051F062-GQR Silicon Laboratories Inc, C8051F062-GQR Datasheet - Page 239

• Manufacturer Part Number: C8051F062-GQR
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F062-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 59
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 336-1214 - DEV KIT FOR F060/F062/F063
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.3.3. Slave Transmitter Mode
Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives
a START followed by data byte containing the slave address and direction bit. If the received slave address
matches the address held in register SMB0ADR, the SMBus0 interface generates an ACK. SMBus0 will
also ACK if the general call address (0x00) is received and the General Call Address Enable bit
(SMB0ADR.0) is set to logic 1. In this case the data direction bit (R/W) will be logic 1 to indicate a "READ"
operation. The SMBus0 interface receives the clock on SCL and transmits one or more bytes of serial
data, waiting for an ACK from the master after each byte. SMBus0 exits slave mode after receiving a
STOP condition from the master.
20.3.4. Slave Receiver Mode
Serial data is received on SDA while the serial clock is received on SCL. The SMBus0 interface receives a
START followed by data byte containing the slave address and direction bit. If the received slave address
matches the address held in register SMB0ADR, the interface generates an ACK. SMBus0 will also ACK if
the general call address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to
logic 1. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The
SMBus0 interface receives one or more bytes of serial data; after each byte is received, the interface
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 20.6. Typical Slave Transmitter Sequence
Interrupt
R
A
Data Byte
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Interrupt
A
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Data Byte
Interrupt
N
Interrupt
P
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