M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 131

MCU 3/5V 0K,PB-FREE 100-QFP

M30800SFP-BL#U5

Manufacturer Part Number
M30800SFP-BL#U5
Description
MCU 3/5V 0K,PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet

Specifications of M30800SFP-BL#U5

Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30800SFP-BL#U5M30800SFP-BL#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30800SFP-BL#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
e
E
1
v
J
6
1 .
0
Triangular wave modulation
C
9
0 .
To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit
(bit 6 at 0308
of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register’s content to the
counter every time timer B2 counter’s content becomes 0000
output specification bit (bit 1 at 0308
B2 counter’s value becomes 0000
frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting
Setting “1” in the effective interrupt output specification bit (bit 1 at 0308
which value of the timer A1 reload control signal to use, “0” or “1”, to cause timer B2’s interrupt request to
occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 0308
An example of U phase waveform is shown in Figure 15.6, and the description of waveform output work-
ings is given below. Set “1” in DU0 (bit 0 at 030A
“0” in DU1 (bit 0 at 030B
output specification bit (bit 1 at 0308
counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter’s content becomes 0000
as many as (setting) times. Furthermore, set “1” in the effective interrupt output specification bit (bit 1 at
0308
rence frequency set counter (030D
interval when the U phase output goes to “H”.
When the timer B2 counter’s content becomes 0000
instance, the content of DU1 (bit 0 at 030B
output shift register (U phase), the content of DUB1 (bit 1 at 030B
are set in the three-phase shift register (U phase). After triangular wave modulation mode is selected,
however, no setting is made in the shift register even though the timer B2 counter’s content becomes
0000
The value of DU0 and that of DUB0 are output to the U terminal (P8
respectively. When the timer A4 counter counts the value written to timer A4 (034F
timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one posi-
tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output
signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for
setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level of the U
phase waveform, which has the opposite phase of the former. The U phase waveform output that started
from the “H” level keeps its level until the timer for setting dead time finishes outputting one-shot pulses
even though the three-phase output shift register’s content changes from “1” to “0” by the effect of the
one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, "0" already
shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L"
level. When the timer B2 counter’s content becomes 0000
value written to timer A4-1 (0307
ishes outputting one-shot pulses, the three-phase shift register’s content is shifted one position, but if the
three-phase output shift register’s content changes from “0” to “1” as a result of the shift, the output level
changes from “L” to “H” without waiting for the timer for setting dead time to finish outputting one-shot
pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the
three-phase output shift register on the U phase side is used, the workings in generating a U phase
waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U
8 /
B
0
0
0
1
A
8
G
u
7
16
16
o r
. g
0 -
), set in the effective interrupt polarity select bit (bit 0 at 0308
.
u
1
0
p
0
, 2
0
2
16
0
0
). Also, set “1” in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 0309
5
Page 118
16
) and set “1” in DUB1 (bit 1 at 030B
f o
3
2
9
16
16
, 0306
16
16
16
can be set by use of the timer B2 counter (030D
), the frequency of interrupt requests that occur every time the timer
). These settings cause a timer B2 interrupt to occur every other
) to set a value in the timer B2 interrupt occurrence frequency set
___
16
16
), and starts outputting one-shot pulses. When timer A4 fin-
) and that of DU0 (bit 0 at 030A
16
15. Three-phase motor control timers’ functions
). And set “0” in DUB0 (bit 1 at 030A
16
, timer A4 starts outputting one-shot pulses. In this
16
, the timer A4 counter starts counting the
16
16
). Also, set “0” in the effective interrupt
. If “0” is set to the effective interrupt
16
16
) and that of DUB0 (bit 1 at 030A
) and set "1" in the interrupt occur-
16
) provides the means to choose
0
) and to the U terminal (P8
16
) are set in the three-phase
16
16
). In this mode, each
, 034E
16
16
___
). In addition, set
) for setting the
___
16
) and when
0).
16
).
16
16
1
___
)
)

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