M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 85

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
9.19 NMI Interrupt
9.20 Key Input Interrupt
e
E
1
v
Figure 9.10 Block diagram of key input interrupt
J
6
1 .
0
An NMI interrupt is generated when the input to the P8
is a non-maskable external interrupt. The pin level can be checked in the port P8
03C4
This pin cannot be used as a normal port input.
Notes:
If the direction register of any of P10
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P10
P10
level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Setting the key input interrupt disable bit (bit 7 at address 03AF
occurring regardless of the setting in the interrupt control register. When “1” is set in the key input interrupt
disable register, there is no input via the port pin even when the direction register is set to input.
C
9
0 .
P10
P10
8 /
P10
B
When not intending to use the NMI function, be sure to connect the NMI pin to V
interrupt is non-maskable. Because it cannot be disabled, the pin must be pulled up.
P10
0
______
0
0
______
7
1
7
6
5
A
4
16
8
G
as A/D input ports. Figure 9.10 shows the block diagram of the key input interrupt. Note that if an “L”
Pull-up
transistor
/KI
/KI
/KI
/KI
u
7
o r
).
. g
0 -
3
2
1
0
u
1
0
p
0
, 2
0
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
2
0
0
5
Page 72
key input interrupt
disable bit
Port P10
register
Port P10
register
Port P10
register
Port P10
f o
3
______
2
9
6
5
4
Port P10
select bit
Port P10
register
7
4
direction
direction
direction
direction register
to P10
4
7
-P10
direction
7
is set for input and a falling edge is input to that port, a key
7
pull-up
5
/NMI pin changes from “H” to “L”. The NMI interrupt
______
Key input interrupt control
16
) to “1” disables key input interrupts from
Interrupt control
register
______
circuit
5
register (bit 5 at address
CC
(address 0093
9. Interrupt Outline
(pulled-up). The NMI
Key input interrupt
request
______
16
)
______
4
to