M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 350

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
1
6
Version
Rev.D3
C
8 /
0
G
o r
Page 204 Making power consumption electricity small --> addition
Page 207 Table 1.28.3
Page 208 Table 1.28.5 Note Change
Page 215 Table 1.28.22
Page 217-220 Figure 1.28.2-1.28.5
Page 219, 220, 222, 223, 225
Page 225, 226 Figure 1.28.10, 1.28.11
Page 227 Figure 1.28.12
Page 230
Page 246 Table 1.29.1
Page 247 Figure 1.29.2
Page 248 Flash memory line 5 change
Page 250 Function outline Line 24 (Parallel ... function ) --> delate
Page 269 Standard serial I/O mode Line 26 externl device --> external device ( programmer)
Page 285 Figure1.31.21
Page 43 Figure1.8.4 Note of the system clock control register 0-->addition
Page 44 Line 4 Note-->addition
Page 45 Table1.8.2 Note-->addition
Page 71 Line 9 "Address match interrupt is not generated with a start instruction of interrupt
Page 73 (6) Precaution of Address mach interrupt-->addition
Page 79 Figure1.11.2 Note-->change
Page 87 Precaution for DMAC-->addition
Page 131 Figure1.16.11 Bit 7-->Must set to "1" in selecting IIC mode.
Page 152 Figure1.20.1 Bit 7-->Must set to "1" in selecting IIC mode.
Page 182 Addition
Page 205 (3) Address match interrupt in Interrupt precautions-->addition
Page 206 (2) DMAC-->addition
Page 207 Precautions for using CLK
Page 210 Table1.28.3 Icc when clock stop Topr=25C
Page 212 Table1.28.6 External clock input HIGH and LOW pulse waidth 22-->20
Page 215, 216 Table1.28.19, 20 t
Page 218 Table1.28.22 t
Page 233 Table1.28.23 Icc when clock stop Topr=25C
Page 235 Table1.28.27 t
Page 238, 239 Table1.28.39, 40 t
Page 240 Table1.28.41 t
Page 241 Table1.28.42 t
Page 242 Figure1.28.15 t
Page 243 Figure1.28.16 t
Page 244, 255 Figure1.28.17 2 wait, Figure1.28.18 3 wait-->addition
Page 246 Figure1.28.19 t
Page 247 Figure1.28.20 Addition
Page 248, 249 Figure1.28.21, 1.28.22 -->addition
u
p
Figure 1.28.4, 1.28.5, 1.28.7, 1.28.8, 1.28.10 addition
routine."-->Delete
3ns, t
d(AD-ALE)
3V of electric characteristics addition
External clock rise and fall time 10-->5
=(tcyc/2-20)ns--> ... -27)ns
h(BCLK-DB)
h(CAS-DB)
d(AD-ALE)
h(BCLK-CAS)
ac3(AD-DB)
ac1(RD-DB)
ac2(RD-DB)
V
t
Refresh timing (self refresh) RAS timing
Data hold --> addition
Package type 144P6Q --> 144P6Q-A
programer --> peripheral unit ( programmer)
RP
T+
expression change
– V
h(BCLK-DB)
w(WR)
=10
-->addition
-->addition, t
-5ns --> -7ns
T-
min-->max, t
min-->max, t
OUT
0ns-->-3ns
Contents for change
9
SCL
/(f
-->addition, t
(BCLK)
pin-->addition
t
t
w(WR)
h(BCLK-DB)
2
-->delete, t
-SCL
C - 8
X2)-20 -->10
su(DB-RD)
ac1(AD-DB)
ac2(AD-DB)
addition, t
4
, SDA
h(BCLK-RD)
o
-5 ns.min --> -7 ns.min
-->change
w(WR)
o
-->change
2
-->t
-SDA
h(BCLK-DB)
9
min-->max
min-->max
-->addition
su(DB-BCLK)
/(f
(BCLK)
4
0ns-->-3ns
Addition
X2)-27
delate
, t
h(BCLK-RD)
0ns -->-
Revision History
19/6/'00
Revision
date