MC68HC711E9VFNE2 Freescale Semiconductor, MC68HC711E9VFNE2 Datasheet - Page 87

• Manufacturer Part Number: MC68HC711E9VFNE2
• Description: IC MCU 8BIT 512BYTES ROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9VFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M68HC11E Family — Rev. 3.2
MOTOROLA
Figure 4-11. MC68HC811E2 System Configuration Register (CONFIG)
Resets:
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch
prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register.
Resets:
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch
prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register.
Single chip:
Single chip:
Expanded:
Expanded:
Bootstrap:
Bootstrap:
Address:
Address:
Read:
Write:
Read:
Write:
Test:
Test:
Figure 4-10. System Configuration Register (CONFIG)
Operating Modes and On-Chip Memory
$103F
$103F
Bit 7
Bit 7
EE3
U
U
0
0
0
0
1
1
= Unimplemented
= Unimplemented
EE2
U
U
6
0
0
0
0
6
1
1
EE1
U
U
5
0
0
0
0
5
1
1
EE0
U
U
4
0
0
0
0
4
1
1
Operating Modes and On-Chip Memory
NOSEC
NOSEC
U
U
U
U
3
1
1
3
1
1
NOCOP
NOCOP
U(L)
U(L)
U(L)
U(L)
U
U
U
U
2
2
ROMON
Technical Data
U
U
U
1
1
1
1
1
1
1
Memory Map
EEON
EEON
Bit 0
Bit 0
U
U
U
U
U
1
1
0
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