DSP56F805FV80E Freescale Semiconductor, DSP56F805FV80E Datasheet - Page 25

• Manufacturer Part Number: DSP56F805FV80E
• Description: IC DSP 80MHZ 31.5K FLASH 144LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxr

Specifications of DSP56F805FV80E

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 71KB (35.5K x 16)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Product: DSPs
• Data Bus Width: 16 bit
• Processor Series: DSP56F8xx
• Core: 56800
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: MAC
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 32
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: PBMCUSLK, DSP56F800DEMO-E
• Interface Type: SCI, SPI
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.4 Flash Memory Characteristics
Freescale Semiconductor
1. X address enable, all rows are disabled when XE = 0
2. Y address enable, YMUX is disabled when YE = 0
3. Sense amplifier enable
4. Output enable, tri-state Flash data out bus when OE = 0
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle
Word Program
Page Erase
Mass Erase
Word program
Standby
Data Invalid State
Page erase
Mass erase
Mode
Read
Mode
Read
Data1 Valid
Data1
XE
H
H
H
H
L
Data Active
1
Table 3-5 Flash Memory Truth Table
YE
Program information block
H
H
L
L
L
Table 3-6 IFREN Truth Table
Erase information block
Read information block
2
Figure 3-3 Signal States
56F805 Technical Data, Rev. 16
Erase both block
Data2 Valid
IFREN = 1
SE
Data2
H
L
L
L
L
3
OE
H
L
L
L
L
4
PROG
Tri-stated
H
L
L
L
L
Data
5
ERASE
Program main memory block
Erase main memory block
Erase main memory block
Read main memory block
H
H
L
L
L
6
IFREN = 0
Data3 Valid
Data Active
Data3
MAS1
H
L
L
L
L
Flash Memory Characteristics
7
NVSTR
H
H
H
L
L
8
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