DSP56F805FV80E Freescale Semiconductor, DSP56F805FV80E Datasheet - Page 37

• Manufacturer Part Number: DSP56F805FV80E
• Description: IC DSP 80MHZ 31.5K FLASH 144LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxr

Specifications of DSP56F805FV80E

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 71KB (35.5K x 16)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Product: DSPs
• Data Bus Width: 16 bit
• Processor Series: DSP56F8xx
• Core: 56800
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: MAC
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 32
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: PBMCUSLK, DSP56F800DEMO-E
• Interface Type: SCI, SPI
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.8 Serial Peripheral Interface (SPI) Timing
Freescale Semiconductor
Operating Conditions:
Cycle time
Master
Slave
Enable lead time
Master
Slave
Enable lag time
Master
Slave
Clock (SCLK) high time
Master
Slave
Clock (SCLK) low time
Master
Slave
Data set-up time required for inputs
Master
Slave
Data hold time required for inputs
Master
Slave
Access time (time to data active from
high-impedance state)
Slave
Disable time (hold time to high-impedance state)
Slave
Data Valid for outputs
Master
Slave (after enable edge)
Data invalid
Master
Slave
Rise time
Master
Slave
Fall time
Master
Slave
1. Parameters listed are guaranteed by design.
Characteristic
V
SS
= V
SSA
= 0 V, V
56F805 Technical Data, Rev. 16
Table 3-12 SPI Timing
DD
= V
DDA
Symbol
t
t
t
t
ELG
t
t
t
ELD
t
= 3.0–3.6 V, T
t
CH
DS
DH
t
t
DV
t
t
CL
DI
C
A
D
R
F
17.6
12.5
24.1
Min
100
4.8
3.7
50
25
25
25
20
—
—
—
—
—
—
—
—
0
0
2
0
0
A
1
= –40° to +85°C, C
Max
15.2
20.4
11.5
10.0
4.5
9.7
9.0
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Serial Peripheral Interface (SPI) Timing
L
Unit
≤
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50pF, f
See Figure
Figure
Figure
Figure
Figure
Figure
OP
3-19, 3-20,
3-19, 3-20,
3-19, 3-20,
3-19, 3-20,
3-19, 3-20,
3-19, 3-20,
3-19, 3-20,
3-19, 3-20,
3-21,
3-21,
3-21,
3-21,
3-21,
3-21,
3-21,
3-21,
Figures
Figures
Figures
Figures
Figures
Figures
Figures
Figures
= 80MHz
3-22
3-22
3-22
3-22
3-22
3-22
3-22
3-22
3-22
3-22
3-22
3-22
3-22
37