DF2148BFA20 Renesas Electronics America, DF2148BFA20 Datasheet - Page 30
![IC H8S MCU FLASH 128K 100-QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
DF2148BFA20
Manufacturer Part Number
DF2148BFA20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BFA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BFA20
HD64F2148BFA20
HD64F2148BFA20
Available stocks
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Quantity
Price
Company:
Part Number:
DF2148BFA20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF2148BFA20IV
Manufacturer:
VISHAY
Quantity:
8 001
Company:
Part Number:
DF2148BFA20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF2148BFA20V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2148BFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.6 Interrupt Sources............................................................................................................... 279
11.7 Usage Notes ...................................................................................................................... 280
Section 12 8-Bit Timer (TMR)
12.1 Features ............................................................................................................................. 287
12.2 Input/Output Pins .............................................................................................................. 290
12.3 Register Descriptions ........................................................................................................ 290
12.4 Operation .......................................................................................................................... 301
12.5 Operation Timing.............................................................................................................. 302
12.6 Operation with Cascaded Connection ............................................................................... 305
Rev. 3.00 Mar 21, 2006 page xxviii of liv
11.5.1 FRC Increment Timing ........................................................................................ 272
11.5.2 Output Compare Output Timing .......................................................................... 273
11.5.3 FRC Clear Timing................................................................................................ 273
11.5.4 Input Capture Input Timing ................................................................................. 274
11.5.5 Buffered Input Capture Input Timing .................................................................. 274
11.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 276
11.5.7 Timing of Output Compare Flag (OCF) setting................................................... 276
11.5.8 Timing of FRC Overflow Flag Setting ................................................................ 277
11.5.9 Automatic Addition Timing................................................................................. 278
11.5.10 Mask Signal Generation Timing .......................................................................... 278
11.7.1 Conflict between FRC Write and Clear ............................................................... 280
11.7.2 Conflict between FRC Write and Increment........................................................ 281
11.7.3 Conflict between OCR Write and Compare-Match ............................................. 282
11.7.4 Switching of Internal Clock and FRC Operation ................................................. 284
11.7.5 Module Stop Mode Setting .................................................................................. 285
12.3.1 Timer Counter (TCNT)........................................................................................ 291
12.3.2 Time Constant Register A (TCORA)................................................................... 291
12.3.3 Time Constant Register B (TCORB) ................................................................... 291
12.3.4 Timer Control Register (TCR) ............................................................................. 291
12.3.5 Timer Control/Status Register (TCSR) ................................................................ 294
12.3.6 Input Capture Register (TICR) ............................................................................ 300
12.3.7 Time Constant Register (TCORC)....................................................................... 300
12.3.8 Input Capture Registers R and F (TICRR, TICRF).............................................. 300
12.3.9 Timer Input Select Register (TISR) ..................................................................... 300
12.4.1 Pulse Output......................................................................................................... 301
12.5.1 TCNT Count Timing............................................................................................ 302
12.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 303
12.5.3 Timing of Timer Output at Compare-Match........................................................ 303
12.5.4 Timing of Counter Clear at Compare-Match ....................................................... 304
12.5.5 TCNT External Reset Timing .............................................................................. 304
12.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 305
........................................................................................ 287
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