DF2148BFA20 Renesas Electronics America, DF2148BFA20 Datasheet - Page 385
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DF2148BFA20
Manufacturer Part Number
DF2148BFA20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BFA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BFA20
HD64F2148BFA20
HD64F2148BFA20
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13.4
13.4.1
The timer connection facility and TMR_X can be used to decode a PWM signal in which 0 and 1
are represented by the pulse width. To do this, a signal in which a rising edge is generated at
regular intervals must be selected as the IHI signal.
The timer counter (TCNT) in TMR_X is set to count the internal clock pulses and to be cleared on
the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for
deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which
uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI
signal (the result of the pulse width decision) at the first compare-match signal B timing after
TCNT is reset by the rise of the IHI signal is output as the PDC signal.
The pulse width setting using TICRR and TICRF of TMR_X can be used to determine the pulse
width decision threshold. Examples of TCR and TCORB settings of TMR_X are shown in tables
13.4 and 13.5, and the PWM decoding timing chart is shown in figure 13.2.
Table 13.4 Examples of TCR Settings
Table 13.5 Examples of TCORB (Pulse Width Threshold) Settings
H'07
H'0F
H'1F
H'3F
H'7F
Bit
7
6
5
4 and 3
2 to 0
Operation
PWM Decoding (PDC Signal Generation)
Abbreviation
CCLR1 and CCLR0 11
CKS2 to CKS0
CMIEB
CMIEA
OVIE
0.8 µs
1.6 µs
3.2 µs
6.4 µs
12.8 µs
: 10 MHz
Contents
0
0
0
001
0.67 µs
1.33 µs
2.67 µs
5.33 µs
10.67 µs
: 12 MHz
Description
Interrupts due to compare-match and overflow
are disabled
TCNT is cleared by the rising edge of the
external reset signal (IHI signal)
Incremented on internal clock ( )
Rev. 3.00 Mar 21, 2006 page 329 of 788
0.5 µs
1 µs
2 µs
4 µs
8 µs
: 16 MHz
Section 13 Timer Connection
0.4 µs
0.8 µs
1.6 µs
3.2 µs
6.4 µs
REJ09B0300-0300
: 20 MHz
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