DF2148BFA20 Renesas Electronics America, DF2148BFA20 Datasheet - Page 41
![IC H8S MCU FLASH 128K 100-QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
DF2148BFA20
Manufacturer Part Number
DF2148BFA20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BFA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BFA20
HD64F2148BFA20
HD64F2148BFA20
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Figure 4.3
Section 5 Interrupt Controller
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Figure 5.7
Figure 5.8
Figure 5.9
Figure 5.10
Figure 5.11
Section 6 Bus Controller (BSC)
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10
Figure 6.11
Figure 6.12
Figure 6.13
Figure 6.14
Figure 6.15
Figure 6.16
Section 7 Data Transfer Controller (DTC)
Figure 7.1
Figure 7.2
Figure 7.3
Operation when SP Value Is Odd ........................................................................ 87
Block Diagram of Interrupt Controller ................................................................ 90
Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0,
Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA,
and WUEMRB..................................................................................................... 99
Block Diagram of Interrupts IRQ7 to IRQ0 ........................................................ 101
Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control
Mode 0 ................................................................................................................. 106
State Transition in Interrupt Control Mode 1....................................................... 107
Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control
Mode 1 ................................................................................................................. 109
Interrupt Exception Handling............................................................................... 111
DTC and Interrupt Controller .............................................................................. 113
Address Break Block Diagram ............................................................................ 115
Address Break Timing Example .......................................................................... 117
Conflict between Interrupt Generation and Disabling ......................................... 118
Block Diagram of Bus Controller ........................................................................ 122
IOS Signal Output Timing ................................................................................... 128
Access Sizes and Data Alignment Control (8-Bit Access Space) ........................ 129
Access Sizes and Data Alignment Control (16-bit Access Space)....................... 130
Bus Timing for 8-Bit, 2-State Access Space........................................................ 131
Bus Timing for 8-Bit, 3-State Access Space........................................................ 132
Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access) ..................... 133
Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)....................... 134
Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................. 135
Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access) ..................... 136
Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)....................... 137
Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................. 138
Example of Wait State Insertion Timing (Pin Wait Mode).................................. 140
Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1) ................ 141
Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) ................ 142
Examples of Idle Cycle Operation ....................................................................... 143
Block Diagram of DTC........................................................................................ 146
Block Diagram of DTC Activation Source Control............................................. 152
DTC Register Information Location in Address Space........................................ 153
Rev. 3.00 Mar 21, 2006 page xxxix of liv
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