DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 50
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 50 of 1208
- Download datasheet (8Mb)
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) .......................... 335
Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer................. 336
Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer..... 337
Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer.................... 338
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer ........ 339
Figure 7.26 Example of Single Address Mode Transfer (Byte Read) ........................................ 340
Figure 7.27 Example of Single Address Mode (Word Read) Transfer....................................... 341
Figure 7.28 Example of Single Address Mode Transfer (Byte Write) ....................................... 342
Figure 7.29 Example of Single Address Mode Transfer (Word Write)...................................... 343
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer..... 344
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer........ 345
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function.................. 346
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function ............... 347
Figure 7.34 Example of Multi-Channel Transfer ....................................................................... 348
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted
Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation....................... 351
Figure 7.37 Example of Procedure for Clearing Full Address Mode ......................................... 352
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt ...................................... 353
Figure 7.39 DMAC Register Update Timing ............................................................................. 354
Figure 7.40 Contention between DMAC Register Update and CPU Read................................. 355
Figure 7.41 Example in which Low Level Is Not Output at TEND Pin ..................................... 357
Section 8 EXDMA Controller (EXDMAC) ...................................................... 359
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode .................. 385
Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and
Figure 8.12 Procedure for Changing Register Settings in Operating Channel ........................... 389
Figure 8.13 Example of Channel Priority Timing ...................................................................... 391
Figure 8.14 Examples of Channel Priority Timing..................................................................... 392
Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer .......................... 393
Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer.................................... 394
Rev.7.00 Mar. 18, 2009 page xlviii of lxvi
REJ09B0109-0700
by NMI Interrupt ..................................................................................................... 350
Block Diagram of EXDMAC.................................................................................. 360
Example of Timing in Dual Address Mode............................................................. 376
Data Flow in Single Address Mode......................................................................... 377
Example of Timing in Single Address Mode .......................................................... 378
Example of Timing in Cycle Steal Mode ................................................................ 380
Examples of Timing in Burst Mode ........................................................................ 381
Examples of Timing in Normal Transfer Mode ...................................................... 382
Example of Timing in Block Transfer Mode .......................................................... 383
Example of Repeat Area Function Operation.......................................................... 384
Block Transfer Mode............................................................................................... 388
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