DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 845
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 845 of 1208
- Download datasheet (8Mb)
16.3.2
ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in I
Bit
7
6
5
4
3
2
Bit Name
BBSY
SCP
SDAO
⎯
SCLO
⎯
I
2
C Bus Control Register B (ICCRB)
Initial Value
0
1
1
1
1
1
R/W
R/W
W
R/W
R/W
R
⎯
Description
Bus Busy
This bit enables to confirm whether the I
occupied or released and to issue start and stop
conditions in master mode. This bit is set to 1 when
the SDA level changes from high to low under the
condition of SCL = high, assuming that the start
condition has been issued. This bit is cleared to 0
when the SDA level changes from low to high
under the condition of SCL = high, assuming that
the stop condition has been issued. Write 1 to
BBSY and 0 to SCP to issue a start condition.
Follow this procedure when also re-transmitting a
start condition. Write 0 to BBSY and 0 to SCP to
issue a stop condition. To issue a start/stop
condition, use the MOV instruction.
Start Condition/Stop Condition Prohibit
The SCP bit controls the issue of start/stop
conditions in master mode.
To issue a start condition, write 1 in BBSY and 0 in
SCP. A retransmit start condition is issued in the
same way. To issue a stop condition, write 0 in
BBSY and 0 in SCP. This bit is always read as 1. If
1 is written, the data is not stored.
Monitors the output level of SDA.
0: When reading, SDA pin outputs low.
1: When reading, SDA pin outputs high.
The write value must always be 1.
Reserved
The write value must always be 1.
This bit monitors SCL output level. When reading
and SCLO is 1, SCL pin outputs high. When
reading and SCLO is 0, SCL pin outputs low.
Reserved
This bit is always read as 1.
2
C control.
Section 16 I
Rev.7.00 Mar. 18, 2009 page 777 of 1136
2
C Bus Interface 2 (IIC2) (Option)
REJ09B0109-0700
2
C bus is
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