HD64F2239FA16 Renesas Electronics America, HD64F2239FA16 Datasheet - Page 254
HD64F2239FA16
Manufacturer Part Number
HD64F2239FA16
Description
IC H8S MCU FLASH 384K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2239FA16
Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239FA16V
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
HD64F2239FA16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 7 Bus Controller
7.7
Burst ROM Interface
With this LSI, external space area 0 can be designated as burst ROM space, and burst ROM
interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM
with burst access capability to be accessed at high speed.
Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH.
Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU
instruction fetches only. One or two states can be selected for burst access.
Note: When the operating frequency ranges from 16 MHz to 20 MHz, the burst ROM interface
is not available.
7.7.1
Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is in accordance
with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state
insertion is possible. One or two states can be selected for the burst cycle, according to the setting
of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst
ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR.
When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when
the BRSTS0 bit is set to 1, burst access of up to 8 words is performed.
The basic access timing for burst ROM space is shown in figures 7.19 and 7.20. The timing shown
in figure 7.19 is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure
7.20 is for the case where both these bits are cleared to 0.
Rev. 6.00 Mar. 18, 2010 Page 192 of 982
REJ09B0054-0600
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