HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 18
Manufacturer Part Number
IC H8S MCU FLASH 256K 120-TQFP
Renesas Electronics America
1.D12312SVTE25V.pdf (341 pages)
Specifications of HD64F2633RTE28
I²C, IrDA, SCI, SmartCard
DMA, POR, PWM, WDT
Number Of I /o
Program Memory Size
256KB (256K x 8)
Program Memory Type
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
A/D 16x10b; D/A 4x8b
-20°C ~ 75°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 1 CPU
Note: * The maximum operating frequency and instruction execution time differ depending on
Differences between the H8S/2600 CPU and the H8S/2000 CPU are as follows.
In addition, there may be defferences in address spaces, EXR register functions, power-down
states, and so on. For details, refer to the relevant microcontroller hardware manual.
Rev. 4.00 Feb 24, 2006 page 2 of 322
Two CPU operating modes
Number of states required for execution
All frequently-used instructions execute in one or two states
Maximum clock frequency:
8/16/32-bit register-register add/subtract: 50 ns
Transition to power-down state by SLEEP instruction
CPU clock speed selection
The MAC register is supported only by the H8S/2600 CPU.
For details, see section 1.4, Register Configuration.
The MAC, CLRMAC, LDMAC, and STMAC instructions are supported only by the
For details, see section 1.6, Instruction Set, and Section 2, Instruction Descriptions.
The number of states required for execution of the MULXU and MULXS instructions.
For details, see section 2.6, Number of States Required for Execution.
Differences between H8S/2600 CPU and H8S/2000 CPU
8-bit register-register multiply:
8-bit register-register divide:
16-bit register-register multiply:
16-bit register-register divide:
150 ns (H8S/2000 CPU: 600 ns)
200 ns (H8S/2000 CPU: 1000 ns)