DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 109
DF2367VF33V
Manufacturer Part Number
DF2367VF33V
Description
IC H8S/2367 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2368VTE34V.pdf
(1044 pages)
Specifications of DF2367VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2.2.23 (3)
CMP (CoMPare)
Operation
ERd – (EAs), set/clear CCR
Assembly-Language Format
CMP.L <EAs>, ERd
Operand Size
Longword
Description
This instruction subtracts the source operand from the contents of a 32-bit register ERd
(destination operand) and sets or clears the condition code bits according to the result. The
contents of the 32-bit register ERd remain unchanged.
Available Registers
ERd: ER0 to ER7
ERs: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
Immediate
Register direct
Addressing
Mode
CMP (L)
Mnemonic
CMP.L
CMP.L
#xx:32, ERd
Operands
ERs, ERd
1st byte
7
1
A
F
1 ers 0 erd
2nd byte
2
0 erd
Condition Code
H: Set to 1 if there is a borrow at bit 27;
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Set to 1 if there is a borrow at bit 31;
3rd byte
Instruction Format
otherwise cleared to 0.
cleared to 0.
cleared to 0.
cleared to 0.
otherwise cleared to 0.
—
I
Rev. 4.00 Feb 24, 2006 page 93 of 322
UI H
—
Section 2 Instruction Descriptions
4th byte
—
IMM
U
5th byte
N
REJ09B0139-0400
Z
6th byte
V
Compare
C
States
No. of
3
1
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