DF2376VFQ33V Renesas Electronics America, DF2376VFQ33V Datasheet - Page 241
![IC H8S/2376 MCU FLASH 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2376VFQ33V
Manufacturer Part Number
DF2376VFQ33V
Description
IC H8S/2376 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2376VFQ33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2376VFQ33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 6.2
ABWCR
ABWn
0
1
(n = 0 to 7)
Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of
the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in
the basic bus interface space.
Chip Select (CS) Assertion Period Extension States: Some external I/O devices require a setup
time and hold time between address and CS signals and strobe signals such as RD, HWR, and
LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are
asserted before and after a basic bus space access cycle.
ASTCR
ASTn
0
1
0
1
Bus Specifications for Each Area (Basic Bus Interface)
Wn2
⎯
0
1
⎯
0
1
WTCRA, WTCRB
Wn1
⎯
0
1
0
1
⎯
0
1
0
1
Wn0
⎯
0
1
0
1
0
1
0
1
⎯
0
1
0
1
0
1
0
1
Bus Width
16
8
Bus Specifications (Basic Bus Interface)
Rev.7.00 Mar. 18, 2009 page 173 of 1136
Section 6 Bus Controller (BSC)
Access
States
2
3
2
3
REJ09B0109-0700
Program Wait
States
0
0
1
2
3
4
5
6
7
0
0
1
2
3
4
5
6
7
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