DF2376VFQ33V Renesas Electronics America, DF2376VFQ33V Datasheet - Page 514
![IC H8S/2376 MCU FLASH 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2376VFQ33V
Manufacturer Part Number
DF2376VFQ33V
Description
IC H8S/2376 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2376VFQ33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2376VFQ33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 Data Transfer Controller (DTC)
Table 9.7
Mode
Normal
Repeat
Block transfer
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 9.8
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev.7.00 Mar. 18, 2009 page 446 of 1136
REJ09B0109-0700
Bus width
Access states
Execution
status
Object to be Accessed
Number of execution states = I · S
Vector read
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation
DTC Execution Status
Number of States Required for Each Execution Status
Vector Read
I
1
1
1
Register Information
Read/Write
J
6
6
6
S
S
S
S
S
S
S
I
J
K
K
L
L
M
Chip
RAM
On-
32
—
1
1
1
1
1
1
I
+ Σ (J · S
ROM
Chip
On-
16
—
1
1
1
1
1
1
J
On-Chip I/O
+ K · S
Registers
—
—
2
8
2
4
2
4
Data Read
K
1
1
N
K
16
—
—
+ L · S
2
2
2
2
2
1
L
—
Data Write
L
1
1
N
) + M · S
2
4
2
4
2
4
External Devices
8
6+2m
6+2m
6+2m
3+m
3+m
—
3
M
Internal
Operations
M
3
3
3
—
2
2
2
2
2
2
16
3+m
3+m
3+m
3+m
3+m
—
3
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