HD6473258P10V Renesas Electronics America, HD6473258P10V Datasheet - Page 170

• Manufacturer Part Number: HD6473258P10V
• Description: MCU 5V 32K PB-FREE 64-DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10V

• Core Size: 8-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• No. Of I/o's: 53
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• Digital Ic Case Style: DIP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/330
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4 Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B
(CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding
enable bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller
for each interrupt. Table 8-3 lists information about these interrupts.
Table 8-3. 8-Bit Timer Interrupts
Interrupt
CMIA
CMIB
OVI
8.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor.
The control bits are set as follows:
(1) In the TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared
(2) In the TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on compare-
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a
pulse width determined by TCORB. No software intervention is required.
when its value matches the constant in TCORA.
match A and to 0 on compare-match B.
OVF
Ø
Description
Requested when CMFA and CMIEA are set
Requested when CMFB and CMIEB are set
Requested when OVF and OVIE are set
Figure 8-11. Clearing of Overflow Flag
When cycle: CPU writes "0" in OVF
T
1
T
163
2
T
3
Priority
High
Low