HD6473258P10V Renesas Electronics America, HD6473258P10V Datasheet - Page 231

MCU 5V 32K PB-FREE 64-DIP

HD6473258P10V

Manufacturer Part Number
HD6473258P10V
Description
MCU 5V 32K PB-FREE 64-DIP
Manufacturer
Renesas Electronics America
Series
H8® H8/325r
Datasheets

Specifications of HD6473258P10V

Core Size
8-Bit
Program Memory Size
32KB (32K x 8)
Oscillator Type
External
Core Processor
H8/300
Speed
10MHz
Connectivity
SCI, UART/USART
Number Of I /o
53
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Operating Temperature
-20°C ~ 75°C
Package / Case
64-DIP
No. Of I/o's
53
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
3
Digital Ic Case Style
DIP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/330
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Peripherals
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473258P10V
Manufacturer:
RENESAS
Quantity:
600
Part Number:
HD6473258P10V
Manufacturer:
RENESAS
Quantity:
1 200
Part Number:
HD6473258P10V
Manufacturer:
HITACHI/日立
Quantity:
20 000
Section 13. E-Clock Interface
13.1 Overview
For interfacing to peripheral devices that require it, the H8/325 series can generate an E clock
output. Special instructions (MOVTPE, MOVFPE) perform data transfers synchronized with the E
clock.
The E clock is created by dividing the system clock (Ø) by 8. The E clock is output at the P4
pin
7
when the P4
DDR bit in the port 4 data direction register (P4DDR) is set to 1. It is output only in
7
the expanded modes (mode 1 and mode 2); it is not output in the single-chip mode. Output begins
immediately after a reset.
When the CPU executes an instruction that synchronizes with the E clock, the address strobe (AS),
the address on the address bus, and the IOS signal are output as usual, but the RD and WR signal
lines and the data bus do not become active until the falling edge of the E clock is detected. The
length of the access cycle for an instruction synchronized with the E clock accordingly varies from
9 to 16 states. Figures 15-1 and 15-2 show the timing in the cases of maximum and minimum
synchronization delay.
It is not possible to insert wait states (T
) during the execution of an instruction synchronized with
w
the E clock by input at the WAIT pin.
227

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