HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 308
![MCU 3/5V 60K PB-FREE 84-PLCC](/photos/19/4/190434/42268236_sml.jpg)
HD64F3337YCP16V
Manufacturer Part Number
HD64F3337YCP16V
Description
MCU 3/5V 60K PB-FREE 84-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16V
Core Size
8-Bit
Program Memory Size
60KB (60K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
No. Of I/o's
74
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
6
No. Of Pwm Channels
2
Digital Ic Case Style
PLCC
Controller Family/series
H8/300
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
COILMASTER
Quantity:
30 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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In receiving, the SCI operates as follows.
1. If an external clock is selected, data is input in synchronization with the input clock. If clock
2. Receive data is shifted into RSR in order from LSB to MSB.
3. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the
Figure 12.16 shows an example of SCI receive operation.
276
output is selected, as soon as the RE bit is set to 1 the SCI begins outputting the serial clock
and inputting data. If clock output is stopped because the ORER bit is set to 1, output of the
serial clock and input of data resume as soon as the ORER bit is cleared to 0.
After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from
RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in
RDR. If the check does not pass (receive error), the SCI operates as indicated in
table 12.10.
Note: Both transmitting and receiving are disabled while a receive error flag is set. The
SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to 1 and the RIE bit in SCR
is set to 1, the SCI requests an ERI (receive-error) interrupt.
When clock output mode is selected, clock output stops when the RE bit is cleared to 0 or the
ORER bit is set to 1. To prevent clock count errors, it is safest to receive one dummy byte and
generate an overrun error.
Serial data
RDRF
ORER
Serial clock
RDRF bit is not set to 1. Be sure to clear the error flag.
RXI
request
Bit 0
Figure 12.16 Example of SCI Receive Operation
RXI interrupt
handler reads
data in RDR and
clears RDRF to 0
Bit 1
1 frame
Bit 7
RXI
request
Bit 0
Bit 1
Bit 6
Bit 7
Overrun error,
ERI request
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