HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 349
![MCU 3/5V 60K PB-FREE 84-PLCC](/photos/19/4/190434/42268236_sml.jpg)
HD64F3337YCP16V
Manufacturer Part Number
HD64F3337YCP16V
Description
MCU 3/5V 60K PB-FREE 84-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16V
Core Size
8-Bit
Program Memory Size
60KB (60K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
No. Of I/o's
74
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
6
No. Of Pwm Channels
2
Digital Ic Case Style
PLCC
Controller Family/series
H8/300
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
COILMASTER
Quantity:
30 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14.1.2
Table 14.1 lists the input and output pins of the host interface module.
Table 14.1 HIF Input/Output Pins
Name
I/O read
I/O write*
Chip select 1
Chip select 2*
Command/data
Data bus
Host interrupt 1
Host interrupt 11
Host interrupt 12
Gate A
Note: * Selection between IOW and EIOW, and between CS
20
STCR. IOW and CS
In this manual, both are referred to as IOW and CS
Input and Output Pins
Abbreviation
IOR
IOW
EIOW
CS
CS
ECS
HA
HDB
HIRQ
HIRQ
HIRQ
GA
1
2
0
20
2
7
–HDB
1
11
12
2
are used when STAC is 0. EIOW and ECS
0
Port
P8
P8
P9
P8
P8
P9
P8
P3
P4
P4
P4
P8
3
4
1
2
5
0
0
7
4
3
5
1
–P3
0
I/O
Input
Input
Input
Input
Input
I/O
Output
Output
Output
Output
2
.
2
Function
Host interface read signal
Host interface write signal
Host interface chip select signal for
IDR1, ODR1, STR1
Host interface chip select signal for
IDR2, ODR2, STR2
Host interface address select signal
In host read access, this signal
selects the status registers (STR1,
STR2) or data registers (ODR1,
ODR2). In host write access to the
data registers (IDR1, IDR2), this
signal indicates whether the host is
writing a command or data.
Host interface data bus (single-chip
mode)
Host interrupt output 1 to host
Host interrupt output 11 to host
Host interrupt output 12 to host
A
and ECS
20
gate control signal output
2
, is by the STAC bit in
2
are used when STAC is 1.
317
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