M3087BFKAGP#U5 Renesas Electronics America, M3087BFKAGP#U5 Datasheet - Page 160
![IC M32C/87B MCU FLASH 144LQFP](/photos/12/43/124312/m3087bfkagp_u5_sml.jpg)
M3087BFKAGP#U5
Manufacturer Part Number
M3087BFKAGP#U5
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKAGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Part Number:
M3087BFKAGP#U5M3087BFKAGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
M3087BFKAGP#U5M3087BFKAGP#U3
Manufacturer:
Renesas Electronics America
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 136 of 587
Figure 12.2
System Clock Control Register 0
b7 b6 b5 b4
NOTES:
10. When stop mode is entered, the CM03 bit becomes 1.
1. Set the CM0 register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. The BCLK, ALE, or "L" signal is output from the P5_3 in memory expansion mode or microprocessor mode. Port P5_3 does not
3. fC32 does not stop running.
8. Change the CM07 bit setting from 0 to 1, after the CM04 bit is set to 1 and the sub clock oscillation stabilizes.
4. To set the CM04 bit to 1, set bits PD8_7 and PD8_6 in the PD8 register to 00b (ports P8_6 and P8_7 in input mode) and the
5. The CM05 bit stops the main clock oscillation when entering low-power consumption mode or on-chip oscillator low-power
6. When the CM05 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). In on-chip
7. Once the CM06 bit is set to 1, it cannot be set to 0 by a program.
9. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to bits CM02, CM05, and CM07 has no effect.
function as an I/O port.
PU25 bit in the PUR2 register to 0 (not pulled up).
consumption mode. The CM05 bit cannot be used to determine whether the main clock stops or not. To stop the main clock
oscillation, set the PLC07 bit in the PLC0 register to 0 and the CM05 bit to 1 after setting the CM07 bit to 1 or setting the CM21
bit in the CM2 register to 1 (on-chip oscillator clock).
When the CM05 bit is set to 1, the XOUT pin outputs "H". Since an on-chip feedback resistor remains ON, the XIN pin is pulled
up to the XOUT pin via the feedback resistor.
oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit is set to 1.
Change the CM07 bit setting from 1 to 0, after the CM05 bit is set to 0 and the main clock oscillation stabilizes.
Do not change the CM07 bit simultaneously with the CM04 or CM05 bit.
b3
b2
CM0 Register
b1
b0
Bit Symbol
CM00
CM01
CM02
CM03
CM04
CM05
CM06
CM07
Symbol
CM0
Clock output function select bits
Peripheral function clock stop
in wait mode bit
XCIN-XCOUT drive capability
select bit
Port XC switch bit
Main clock (XIN-XOUT)
stop bit
Watchdog timer
function select bit
CPU clock select bit 0
(5, 9)
(10)
(1)
Bit Name
(9)
(8, 9)
Address
0006h
(2)
b1 b0
0 0: I/O port P5_3
0 1: Outputs fC
1 0: Outputs f8
1 1: Outputs f32
0: Peripheral clocks do not stop in wait mode
1: Peripheral clocks stop in wait mode
0: Low
1: High
0: I/O port function
1: XCIN-XCOUT oscillation function
0: Main clock oscillates
1: Main clock stops
0: Watchdog timer interrupt
1: Reset
0: Clock selected by the CM21 bit divided by
1: Sub clock
the MCD register
(7)
(2)
Function
(6)
(4)
After Reset
0000 1000b
(3)
12. Watchdog Timer
RW
RW
RW
RW
RW
RW
RW
RW
RW
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