M3087BFKAGP#U5 Renesas Electronics America, M3087BFKAGP#U5 Datasheet - Page 393
![IC M32C/87B MCU FLASH 144LQFP](/photos/12/43/124312/m3087bfkagp_u5_sml.jpg)
M3087BFKAGP#U5
Manufacturer Part Number
M3087BFKAGP#U5
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKAGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M3087BFKAGP#U5M3087BFKAGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
M3087BFKAGP#U5M3087BFKAGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 369 of 587
Figure 22.37
ch1 generation clock
ch2 generation clock
ch3 generation clock
Reception
Transmission
i = 0 to 3
CCS3 and CCS2: bits in the CCS register
CKDIR: bit in the G1MR register
TXSL, RXSL: bits in the G1EMR register
SIO1TR, G1TOR: bits in the IIO3IR register
SIO1RR, G1RIR: bits in the IIO2IR register
NOTE:
Clock input to
ISCLK1 pin
1. After a clock, which is selected in the G1BCR0 register, is supplied to the registers, each register value becomes the after reset value.
j = 0,1
Group 1 Communication Function Block Diagram
Receive data
input to ISRXD1
selector
Clock
f2n
CCS3 and CCS2
f1
f8
00
01
10
11
0
1
CKDIR
Polarity
invert
Transmit
register
register
G1RI
G1TB
Shift
shift
control
Clock
0
1
generation circuit
generation circuit
RXSL
G1CMPi
G1CMPi
G1CMPi
G1CMPi
Start bit
Stop bit
Bit insert
circuit
Comparator
Latch
register
G1DR
Shift
G1MSKj
G1MSKi
Transmission
control circuit
Bit delete
detection
verifying
verifying
Reception control
Start bit
Stop bit
circuit
circulation
circuit
CRC
TXSL
HDLC transmit interrupt request
(G1TOR)
0
1
Transmit interrupt request
(SIO1TR)
circulation
Polarity
Serial clock output
from ISCLK1 pin
Receive
invert
register
register
G1RB
circuit
CRC
Shift
Receive interrupt
request (SIO1RR)
HDLC receive
interrupt request
(G1RIR)
shift
G1TO
Transmit data
output from
ISTXD1
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