M3087BFKAGP#U5 Renesas Electronics America, M3087BFKAGP#U5 Datasheet - Page 48
![IC M32C/87B MCU FLASH 144LQFP](/photos/12/43/124312/m3087bfkagp_u5_sml.jpg)
M3087BFKAGP#U5
Manufacturer Part Number
M3087BFKAGP#U5
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKAGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M3087BFKAGP#U5M3087BFKAGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
M3087BFKAGP#U5M3087BFKAGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 24 of 587
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.8.1
2.1.8.2
2.1.8.3
2.1.8.4
2.1.8.5
2.1.8.6
R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into
high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers.
R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1.
A0 and A1 are 24-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer,
arithmetic and logic operations.
SB is a 24-bit register used for SB-relative addressing.
FB is a 24-bit register used for FB-relative addressing.
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP.
Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an
interrupt sequence efficiently.
INTB is a 24-bit register indicating the starting address of a relocatable interrupt vector table.
PC is 24 bits wide and indicates the address of the next instruction to be executed.
FLG is a 16-bit register indicating the CPU state.
General Registers
The C flag indicates whether or not carry or borrow has been generated after executing an instruction.
The D flag is for debugging only. Set it to 0.
The Z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0.
The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0.
Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1.
The O flag becomes 1 when an arithmetic operation results in an overflow; otherwise becomes 0.
Data Registers (R0, R1, R2, and R3)
Address Registers (A0 and A1)
Static Base Register (SB)
Frame Base Register (FB)
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Interrupt Table Register (INTB)
Program Counter (PC)
Flag Register (FLG)
Carry Flag (C)
Debug Flag (D)
Zero Flag (Z)
Sign Flag (S)
Register Bank Select Flag (B)
Overflow Flag (O)
2. Central Processing Unit (CPU)
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