M30620FCAFP#D3 Renesas Electronics America, M30620FCAFP#D3 Datasheet - Page 221
![IC M16C MCU FLASH 128K 100LQFP](/photos/28/61/286112/100-bqfp__prqp0100jb-a_sml.jpg)
M30620FCAFP#D3
Manufacturer Part Number
M30620FCAFP#D3
Description
IC M16C MCU FLASH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30620FCAFP#D3
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Timing (Vcc = 3V)
1-200
Figure 1.23.12. V
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Write timing
Read timing
BHE
BCLK
CSi
WRH
BCLK
CSi
ADi
/DBi
ALE
RD
ADi
/DBi
BHE
ALE
WR,WRL,
ADi
ADi
60ns.max
t
60ns.max
t
d(BCLK–ALE)
t
d(BCLK–ALE)
CC
d(AD–ALE) (tcyc/2–45)ns.min
= 3V timing diagram (5)
(tcyc/2–60)ns.min
t
t
t
h(ALE–AD)
d(BCLK–AD)
d(AD–ALE)
t
t
t
60ns.max
Measuring conditions :
d(BCLK–CS)
d(BCLK–AD)
60ns.max
d(BCLK–CS)
50ns.min
60ns.max
60ns.max
• V
• Input timing voltage : Determined with V
• Output timing voltage : Determined with V
CC
t
h(BCLK–ALE)
Address
=3V
Address
–4ns.min
t
h(BCLK–ALE)
–4ns.min
t
d(AD–RD)
0ns.min
t
t
d(BCLK–WR)
t
d(BCLK–DB)
80ns.max
t
d(BCLK–RD)
60ns.max
60ns.max
d(AD–WR)
0ns.min
t
dz(RD–AD)
8ns.max
tcyc
tcyc
tac3(RD–DB)
(tcyc*3/2–80)ns.min
Data output
t
d(DB–WR)
IL
=0.48V,V
OL
=1.5V,V
(tcyc/2)ns.min
(tcyc/2)ns.min
t
h(WR–CS)
t
h(RD–CS)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
t
SU(DB–RD)
Data input
80ns.min
IH
OH
=1.5V
=1.5V
(tcyc/2)ns.min
(tcyc/2)ns.min
t
(tcyc/2)ns.min
h(BCLK–WR)
t
t
t
t
h(WR–DB)
h(WR–AD)
h(BCLK–RD)
0ns.min
h(RD–AD)
0ns.min
t
h(RD–DB)
0ns.min
V
M16C / 62A Group
CC
t
Mitsubishi microcomputers
h(BCLK–AD)
t
t
t
h(BCLK–AD)
4ns.min
h(BCLK–DB)
4ns.min
t
4ns.min
h(BCLK–CS)
4ns.min
h(BCLK–CS)
4ns.min
Address
Address
= 3V
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