M30620FCAFP#D3 Renesas Electronics America, M30620FCAFP#D3 Datasheet - Page 423
![IC M16C MCU FLASH 128K 100LQFP](/photos/28/61/286112/100-bqfp__prqp0100jb-a_sml.jpg)
M30620FCAFP#D3
Manufacturer Part Number
M30620FCAFP#D3
Description
IC M16C MCU FLASH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30620FCAFP#D3
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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2-104
UART
Figure 2.5.21 Relationship between transfer clock and receive data
2.5.7 Error-permitted range range of transfer baud
During reception, the receive data input to the R
Accordingly, in order to receive data correctly, the stop bit must be input when the transfer clock of one-
set receive data rises last. Figure 2.5.21 shows the relationship between the transfer clock and receive
data.
<1ST-8DATA-1SP>
(Receive data)
RxD
i
When the transfer rate of
the receive data is faster
than the rate of the transfer
clock on the receiver side
When the transfer rate of
the receive data is slower
than the rate of the transfer
clock on the receiver side
(Receiver side)
Transfer clock
1 period of BRGi's count source (Maximum)
••• According to the condition of the input timing,
a maximum of this period ( ) can be omitted.
ST
ST
At the falling edge of ST, the transfer clock is
generated, and reception starts.
1 clock
D
D
0
0
X
Di pin is taken at the rising edge of the transfer clock.
9.5 clocks
8 clocks
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D
7
ST : Start bit
SP : Stop bit
D
7
SP
1 clock
SP
M16C / 62A Group
Mitsubishi microcomputers
SP must be detected at
this last rising edge of
the transfer clock.
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