UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 214

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

14.4 Operation of Low-Voltage Detector
212
The low-voltage detector can be used in the following two modes.
The operation is set as follows.
(1) When used as reset
Used as reset
Compares the supply voltage (V
V
Used as interrupt
Compares the supply voltage (V
when V
DD
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to instigate a wait of at least 0.2 ms.
<5> Wait until “supply voltage (V
<6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (V
Figure 14-4 shows the timing of generating the internal reset signal of the low-voltage detector. Numbers <1>
to <6> in this figure correspond to <1> to <6> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
< V
When starting operation
When stopping operation
Either of the following procedures must be executed.
When using 8-bit memory manipulation instruction: Write 00H to LVIM.
When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and LVION to 0 in that order.
DD
register (LVIS).
voltage (V
LVI
, and releases internal reset when V
< V
2. If supply voltage (V
LVI
after the processing in <3>.
signal is not generated.
.
LVI
)).
CHAPTER 14 LOW-VOLTAGE DETECTOR
DD
DD
) and detection voltage (V
DD
) and detection voltage (V
DD
) ≥ detection voltage (V
) ≥ detection voltage (V
User’s Manual U16994EJ6V0UD
DD
≥ V
LVI
.
LVI
LVI
LVI
)” at bit 0 (LVIF) of LVIM is confirmed.
LVI
), and generates an internal reset signal when
), and generates an interrupt signal (INTLVI)
) when LVIMD is set to 1, an internal reset
DD
) < detection