UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 239

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

(2) Flash protect command register (PFCMD)
(3) Flash status register (PFS)
Caution Interrupt servicing cannot be executed in self programming mode.
Caution Check FPRERR using a 1-bit memory manipulation instruction.
If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an
Writing FLPMC is enabled only when a write operation is performed in the following specific sequence.
<1> Write a specific value to PFCMD (A5H)
<2> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is invalid)
<3> Write the inverted value of the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is
<4> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is valid)
This rewrites the value of the register, so that the register cannot be written illegally.
Occurrence of an illegal write operation can be checked by bit 0 (FPRERR) of the flash status register (PFS).
Check FPRERR using a 1-bit memory manipulation instruction.
A5H must be written to PFCMD each time the value of FLPMC is changed.
PFCMD can be set by an 8-bit memory manipulation instruction.
Reset signal generation makes PFCMD undefined.
If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct
sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error
occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1.
When FPRERR is 1, it can be cleared to 0 by writing 0 to it.
Errors that may occur during self programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
VCERR or WEPRERR can be cleared by writing 0 to them.
All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly.
PFS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears PFS to 00H.
operation to write the flash programming mode control register (FLPMC) may have a serious effect on the
system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop
inadvertently.
Address: FFA0H
PFCMD
invalid)
Symbol
servicing (by executing the DI instruction while MK0 = FFH) between the points before
executing the specific sequence that sets self programming mode and after executing the
specific sequence that changes the mode to the normal mode.
Figure 16-11. Format of Flash Protect Command Register (PFCMD)
REG7
7
After reset: Undefined
REG6
6
CHAPTER 16 FLASH MEMORY
REG5
User’s Manual U16994EJ6V0UD
5
REG4
W
4
REG3
3
REG2
2
REG1
1
REG0
Disable interrupt
0
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