UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 494
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
460
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
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Quantity:
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Address: FF88H After reset: 00H R/W
CSIM11
Notes 1.
Symbol
7.
8.
2.
3.
4.
5.
6.
TRMD11
SSE11
DIR11
Bit 0 is a read-only bit.
To use P02/SO11, P04/SCK11, and P05/SSI11/TI001 as general-purpose ports, set CSIM11 in the default
status (00H).
Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset.
Do not rewrite TRMD11 when CSOT11 = 1 (during serial communication).
The SO11 output (see Figure 16-2) is fixed to the low level when TRMD11 is 0. Reception is started when
data is read from SIO11.
Do not rewrite SSE11 when CSOT11 = 1 (during serial communication).
Before setting this bit to 1, fix the SSI11 pin input level to 0 or 1.
Do not rewrite DIR11 when CSOT11 = 1 (during serial communication).
CSOT11
CSIE11
CSIE11
0
<7>
Note 5
0
1
1
0
1
0
1
0
1
Notes 6, 7
Note 8
Note 4
Figure 16-4. Format of Serial Operation Mode Register 11 (CSIM11)
Disables operation
Enables operation
Receive mode (transmission disabled).
Transmit/receive mode
SSI11 pin is not used
SSI11 pin is used
MSB
LSB
Communication is stopped.
Communication is in progress.
TRMD11
6
Note 1
SSE11
Note 2
5
and asynchronously resets the internal circuit
Operation control in 3-wire serial I/O mode
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
DIR11
4
Transmit/receive mode control
Communication status flag
SSI11 pin use selection
First bit specification
3
0
2
0
Note 3
.
1
0
CSOT11
0
494
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