UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 977

• Manufacturer Part Number: UPD78F0533AGB-GAH-AX
• Description: MCU 8BIT 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0533AGB-GAH-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
3rd Edition
Edition
Addition of Notes 2 and 5 to and modification of Note 3 in Figure 17-3 Format of
Serial Status Register 0 (CSIS0) (1/2)
Modification of Note in Figure 17-5 Format of Divisor Selection Register 0
(BRGCA0)
Addition of Note 1 to Table 18-2 Selection Clock Setting
Modification of Table 18-4 Bit Definitions of Main Extension Code
Modification of Figure 18-27 Example of Master to Slave Communication and
Figure 18-28 Example of Slave to Master Communication
Modification of Note 1 in Figure 22-3 HALT Mode Release by Interrupt Request
Generation
Addition of Caution 5 to Table 22-3 Operating Statuses in STOP Mode
Modification of Note 2 in Figure 22-5 Operation Timing When STOP Mode Is
Released (When Unmasked Interrupt Request Is Generated)
Modification of Note in Figure 22-6 STOP Mode Release by Interrupt Request
Generation
Modification of Figure 23-1 Block Diagram of Reset Function
Modification of Notes 3 and 4 in Table 23-2 Hardware Statuses After Reset
Acknowledgment (1/4)
Modification of Figure 24-1 Block Diagram of Power-on-Clear Circuit
Modification of Notes 1 and 2 in and addition of Note 3 to Figure 24-2 Timing of
Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage
Detector (1/2)
Modification of Note 1 in Figure 24-2 Timing of Generation of Internal Reset
Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2)
Addition of Note to 25.1 Functions of Low-Voltage Detector
Modification of Note 4 in and addition of Caution 4 in Figure 25-2 Format of Low-
Voltage Detection Register (LVIM)
Addition of Note 2 and Caution 4 to Figure 25-3 Format of Low-Voltage Detection
Level Selection Register (LVIS)
Modification of Figure 25-9 Example of Software Processing After Reset Release
Modification of caution in 26.1 (2) 0081H/1081H
Modification of Note 1 in “Address: 0081H/1081H” in Figure 26-1 Format of Option
Byte (2/2)
Modification of Table 27-1 Internal Memory Size Switching Register Settings
Modification of Caution 2 in 27.2 Internal Expansion RAM Size Switching
Register
Modification of Table 27-2 Internal Expansion RAM Size Switching Register
Settings
Modification of caution in 27.8 Security Settings
Addition of Table 27-13 Processing Time for Self Programming Library
(Conventional-specification Products (
Addition of Table 27-15. Interrupt Response Time for Self Programming Library
(Conventional-specification Products (
Modification of Caution in 28.1 Connecting QB-MINI2 to
78F0503DA
Addition of Caution in Figure 28-3 Connection of FLMD0 Pin for Self
Programming by Means of On-Chip Debugging
Description
μ
μ
PD78F05xx and 78F05xxD))
PD78F05xx and 78F05xxD))
μ
PD78F0503D and
APPENDIX E REVISION HISTORY
CHAPTER 17 SERIAL
INTERFACE CSIA0
CHAPTER 18 SERIAL
INTERFACE IIC0
CHAPTER 22
STANDBY FUNCTION
CHAPTER 23 RESET
FUNCTION
CHAPTER 24 POWER-
ON-CLEAR CIRCUIT
CHAPTER 25 LOW-
VOLTAGE DETECTOR
CHAPTER 26 OPTION
BYTE
CHAPTER 27 FLASH
MEMORY
CHAPTER 28 ON-
CHIP DEBUG
FUNCTION
(
78F0503DA ONLY)
μ
PD78F0503D and
Chapter
(3/4)
977