UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 677
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
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Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
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78K0/Kx2
(2) STOP mode release
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Notes 1. When AMPH = 1
The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization
time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt
acknowledgment is disabled, the next address instruction is executed.
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
2. The wait time is as follows:
Figure 22-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request Is
• When vectored interrupt servicing is carried out:
• When vectored interrupt servicing is not carried out:
STOP mode
Generated)
STOP mode release
Wait for oscillation accuracy
(oscillation stabilization time set by OSTS)
stabilization (86 to 361 s)
Supply of the CPU clock is stopped (4.06 to 16.12 s)
Supply of the CPU clock is stopped (160 external clocks)
HALT status
Internal high-speed
Wait
oscillation clock
Wait
Note2
Note2
Clock switched by software
Clock switched by software
17 or 18 clocks
11 or 12 clocks
CHAPTER 22 STANDBY FUNCTION
High-speed system clock
High-speed system clock
High-speed system clock
Note1
Note1
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