SAF-XE167F-96F80L AC Infineon Technologies, SAF-XE167F-96F80L AC Datasheet - Page 63

• Manufacturer Part Number: SAF-XE167F-96F80L AC
• Description: IC MCU 16BIT FLASH 144-LQFP
• Manufacturer: Infineon Technologies
• Series: XE16xr

Specifications of SAF-XE167F-96F80L AC

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 82K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000450816

3.10
For analog signal measurement, up to two 10-bit A/D converters (ADC0, ADC1) with
16 + 8 multiplexed input channels and a sample and hold circuit have been integrated
on-chip. They use the successive approximation method. The sample time (to charge
the capacitors) and the conversion time are programmable so that they can be adjusted
to the external circuit. The A/D converters can also operate in 8-bit conversion mode,
further reducing the conversion time.
Several independent conversion result registers, selectable interrupt requests, and
highly flexible conversion sequences provide a high degree of programmability to meet
the application requirements. Both modules can be synchronized to allow parallel
sampling of two input channels.
For applications that require more analog input channels, external analog multiplexers
can be controlled automatically.
For applications that require fewer analog input channels, the remaining channel inputs
can be used as digital input port pins.
The A/D converters of the XE167 support two types of request sources which can be
triggered by several internal and external events.
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•
In addition, the conversion of a specific channel can be inserted into a running sequence
without disturbing that sequence. All requests are arbitrated according to the priority
level assigned to them.
Data reduction features, such as limit checking or result accumulation, reduce the
number of required CPU access operations allowing the precise evaluation of
analoginputs (high conversion rate) even at a low CPU speed.
The Peripheral Event Controller (PEC) can be used to control the A/D converters or to
automatically store conversion results to a table in memory for later evaluation, without
requiring the overhead of entering and exiting interrupt routines for each data transfer.
Each A/D converter contains eight result registers which can be concatenated to build a
result FIFO. Wait-for-read mode can be enabled for each result register to prevent the
loss of conversion data.
In order to decouple analog inputs from digital noise and to avoid input trigger noise,
those pins used for analog input can be disconnected from the digital input stages under
software control. This can be selected for each pin separately with registers P5_DIDIS
and P15_DIDIS (Port x Digital Input Disable).
The Auto-Power-Down feature of the A/D converters minimizes the power consumption
when no conversion is in progress.
Data Sheet
Parallel requests are activated at the same time and then executed in a predefined
sequence.
Queued requests are executed in a user-defined sequence.
A/D Converters
61
XE166 Family Derivatives
Functional Description
V2.1, 2008-08
XE167x