SAF-TC1130-L150EB-G BB Infineon Technologies, SAF-TC1130-L150EB-G BB Datasheet - Page 39

• Manufacturer Part Number: SAF-TC1130-L150EB-G BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB-G BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 144 KB
• Interface Type: 3xASC, 2xSSC, I2C, 2xMLI, Ethernet 10, 100 Mbits, s, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 9
• Operating Supply Voltage: 1.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-LBGA-208
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 144.0 KByte
• Can Nodes: 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: FT1130L150EBGBBXP; SAF-TC1130-L150EB-GBB; SAF-TC1130-L150EB-GBBINTR; SAF-TC1130-L150EB-GBBTR; SAF-TC1130-L150EB-GBBTR; SAFTC1130L150EBBBXT; SP000106119; SP000106538; SP000743584

3.6
The Direct Memory Access Controller executes DMA transactions from a source
address location to a destination address location, without intervention of the CPU. One
DMA transaction is controlled by one DMA channel. Each DMA channel has assigned
its own channel register set. The total of 8 channels are provided by one DMA sub-block.
The DMA module is connected to 3 bus interfaces in TC1130, the Flexible Peripheral
Interconnect Bus (FPI), the DMA Bus and the Micro Link Bus. It can do transfers on each
of the buses as well as between the buses.
In addition, it bridges accesses from the Flexible Peripheral Interconnect Bus to the
peripherals on the DMA Bus, allowing easy access to these peripherals by CPU. Clock
control, address decoding, DMA request wiring, and DMA interrupt service request
control are implementation specific and managed outside the DMA controller kernel.
Features:
• 8 independent DMA channels
• Programmable priority of the DMA sub-block on the bus interfaces
• Buffer capability for move actions on the buses (min. 1 move per bus is buffered).
• Individually programmable operation modes for each DMA channel
• Full 32-bit addressing capability of each DMA channel
• Programmable data width of a DMA transaction: 8-bit, 16-bit, or 32-bit
• Micro Link supported
• Register set for each DMA channel
• Flexible interrupt generation (the service request node logic for the MLI channels is
• All buses/interfaces connected to the DMA module must work at the same frequency
• Read/write requests of the FPI Bus Side to the Remote Peripherals are bridged to the
Data Sheet
also implemented in the DMA module)
DMA Bus (only the DMA is master on the DMA bus)
– Up to 8 selectable request inputs per DMA channel
– Programmable priority of DMA channels within a DMA sub-block (2 levels)
– Software and hardware DMA request generation
– Hardware requests by selected peripherals and external inputs
– Single mode: stops and disables DMA channel after a predefined number of DMA
– Continuous mode: DMA channel remains enabled after a predefined number of
– Programmable address modification
– 4-Gbyte address range
– Support of circular buffer addressing mode
– Source and destination address register
– Channel control and status register
– Transfer count register
transfers
DMA transfers; DMA transaction can be repeated.
Direct Memory Access (DMA)
33
Functional Description
V1.1, 2008-12
TC1130