SAK-TC1797-512F180E AC Infineon Technologies, SAK-TC1797-512F180E AC Datasheet - Page 22
SAK-TC1797-512F180E AC
Manufacturer Part Number
SAK-TC1797-512F180E AC
Description
IC MCU 32BIT FLASH 416-BGA
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet
1.SAK-TC1797-512F180E_AC.pdf
(190 pages)
Specifications of SAK-TC1797-512F180E AC
Core Processor
TriCore
Core Size
32-Bit
Speed
180MHz
Connectivity
ASC, CAN, EBI/EMI, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
219
Program Memory Size
4MB (4M x 8)
Program Memory Type
FLASH
Ram Size
224K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 48x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
416-BGA
Packages
PG-BGA-416
Max Clock Frequency
180.0 MHz
Sram (incl. Cache)
224.0 KByte
Can Nodes
4
A / D Input Lines (incl. Fadc)
48
Program Memory
4.0 MB
For Use With
B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SP000432392
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2.3
The TC1797 microcontroller offers several versatile on-chip system peripheral units
such as DMA controller, embedded Flash module, interrupt system and ports.
2.3.1
The TC1797 includes a programmable interrupt system with the following features:
Features
•
•
•
•
2.3.2
The TC1797 includes a fast and flexible DMA controller with 16 independant DMA
channels (two DMA Move Engines).
Features
•
•
•
•
•
•
•
Data Sheet
Fast interrupt response
Independent interrupt systems for CPU and PCP
Each SRN can be mapped to the CPU or PCP interrupt system
Flexible interrupt-prioritizing scheme with 255 interrupt priority levels per interrupt
system
8 independent DMA channels
– 8 DMA channels in the DMA Sub-Block
– Up to 16 selectable request inputs per DMA channel
– 2-level programmable priority of DMA channels within the DMA Sub-Block
– Software and hardware DMA request
– Hardware requests by selected on-chip peripherals and external inputs
3-level programmable priority of the DMA Sub-Block at the on chip bus interfaces
Buffer capability for move actions on the buses (at least 1 move per bus is buffered)
Individually programmable operation modes for each DMA channel
– Single Mode: stops and disables DMA channel after a predefined number of DMA
– Continuous Mode: DMA channel remains enabled after a predefined number of
– Programmable address modification
– Two shadow register modes (with / w/o automatic re-set and direct write access).
Full 32-bit addressing capability of each DMA channel
– 4 Gbyte address range
– Data block move supports > 32 Kbyte moves per DMA transaction
– Circular buffer addressing mode with flexible circular buffer sizes
Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
Register set for each DMA channel
transfers
DMA transfers; DMA transaction can be repeated
On-Chip System Units
Flexible Interrupt System
Direct Memory Access Controller
18
Introduction
V1.1, 2009-04
TC1797
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