SAK-TC1796-256F150E BE Infineon Technologies, SAK-TC1796-256F150E BE Datasheet - Page 46

• Manufacturer Part Number: SAK-TC1796-256F150E BE
• Description: IC MCU 32BIT FLASH 416-BGA
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BE

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: ASC, JTAG, MLI, MSC, SSC
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 260
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel) / 10 bit, 4 Channel
• Packages: P-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000438972

Note: Although the polynomial above is used for generation, the generation algorithm
3.8
The TC1796 interrupt system provides a flexible and time-efficient means for processing
interrupts. An interrupt request can be serviced either by the CPU or by the Peripheral
Control Processor (PCP). These units are called “Service Providers”. Interrupt requests
are called “Service Requests” rather than “Interrupt Requests” in this document because
they can be serviced by either of the Service Providers.
Each peripheral in the TC1796 can generate service requests. Additionally, the Bus
Control Units, the Debug Unit, the PCP, and even the CPU itself can generate service
requests to either of the two Service Providers.
As shown in
connected to one or more Service Request Nodes (SRN). Each SRN contains a Service
Request Control Register. Two arbitration buses connect the SRNs with two Interrupt
Control Units, which handle interrupt arbitration among competing interrupt service
requests, as follows:
•
•
The PCP2 can make service requests directly to itself (via the PICU), or it can make
service requests to the CPU. The Debug Unit can generate service requests to the PCP2
or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can
make service requests to the PCP. The CPU Service Request Nodes are activated
through software.
Depending on the selected system clock frequency
per arbitration cycle must be selected as follows:
•
•
Data Sheet
The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and
administers the CPU Interrupt Arbitration Bus.
The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP2
and administers the PCP2 Interrupt Arbitration Bus.
f
f
SYS
SYS
differs from the one that is used by the Ethernet protocol.
< 60MHz: ICR.CONECYC = 1 and PCP_ICR.CONECYC = 1
> 60MHz: ICR.CONECYC = 0 and PCP_ICR.CONECYC = 0
Interrupt System
Figure
7, each TC1796 unit that can generate service requests is
46
f
SYS
, the number of
Functional Description
f
SYS
V1.0, 2008-04
clock cycles
TC1796