PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 131

• Manufacturer Part Number: PIC17C756-16/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

14.4
The Synchronous Slave mode differs from the Master
mode, in the fact that the shift clock is supplied exter-
nally at the TX/CK pin (instead of being supplied inter-
nally in the Master mode). This allows the device to
transfer or receive data in the SLEEP mode. The Slave
mode is entered by clearing the CSRC (TXSTA<7>) bit.
14.4.1
The operation of the SYNC Master and Slave modes
are identical except in the case of the SLEEP mode.
If two words are written to TXREG and then the SLEEP
instruction executes, the following will occur. The first
word will immediately transfer to the TSR and will trans-
mit as the shift clock is supplied. The second word will
remain in TXREG. TXIF will not be set. When the first
word has been shifted out of TSR, TXREG will transfer
the second word to the TSR and the TXIF flag will now
be set. If TXIE is enabled, the interrupt will wake the
chip from SLEEP and if the global interrupt is enabled,
then the program will branch to the interrupt vector
(0020h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1.
2.
3.
4.
5.
6.
7.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN), allows transmission to
start sooner than doing these two events in the reverse
order.
Note:
2000 Microchip Technology Inc.
Enable the synchronous slave serial port by set-
ting the SYNC and SPEN bits and clearing the
CSRC bit.
Clear the CREN bit.
If interrupts are desired, then set the TXIE bit.
If 9-bit transmission is desired, then set the TX9
bit.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Start transmission by loading data to TXREG.
Enable the transmission by setting TXEN.
USART Synchronous Slave Mode
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is re-
enabled.
USART SYNCHRONOUS SLAVE
TRANSMIT
14.4.2
Operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode. Also, SREN is a “don't care” in Slave mode.
If receive is enabled (CREN) prior to the SLEEP instruc-
tion, then a word may be received during SLEEP. On
completely receiving the word, the RSR will transfer the
data to RCREG (setting RCIF) and if the RCIE bit is set,
the interrupt generated will wake the chip from SLEEP.
If the global interrupt is enabled, the program will
branch to the interrupt vector (0020h).
Steps to follow when setting up a Synchronous Slave
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
Note:
Enable the synchronous master serial port by
setting the SYNC and SPEN bits and clearing
the CSRC bit.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
To enable reception, set the CREN bit.
The RCIF bit will be set when reception is com-
plete and an interrupt will be generated if the
RCIE bit was set.
Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
Read the 8-bit received data by reading
RCREG.
If any error occurred, clear the error by clearing
the CREN bit.
To abort reception, either clear the SPEN
bit, or the CREN bit (when in Continuous
Receive mode). This will reset the receive
logic, so that it will be in the proper state
when receive is re-enabled.
USART SYNCHRONOUS SLAVE
RECEPTION
PIC17C7XX
DS30289B-page 131